code wiki / _hdl_build / nx_fpga_cpu_gate.nx

nx_fpga_cpu_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_cpu_gate.nx

10298 B172 linesdepth 7pulls 16 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 9 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_decode.nx nx_fpga_alu.nx nx_fpga_cmp.nx nx_fpga_shift.nx nx_fpga_regfile.nx rv64im_min_alu.nx nx_syscalls.nx nx_fpga_cpu_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_decode.nxnx_fpga_alu.nxnx_fpga_cmp.nxnx_fpga_shift.nxnx_fpga_regfile.nxrv64im_min_alu.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap fab_build_decode r9_sub r9_msel0 r9_msel1 r9_right r9_arith r9_uns r9_class sys_mmap ↻ fab_build_alu fl_gate_to_lut4 fl_gate_ref lut4_index fab_parity3_init fab_maj3_init fab_build_cmp fl_gate_to_lut4 ↻ fab_parity3_init ↻ fab_maj3_init ↻ fab_build_shifter fl_gate_to_lut4 ↻ sys_mmap ↻ seq_build_regfile fl_gate_to_lut4 ↻ rf_addr_inputs rf_ncells rf_write seq_tick seq_eval fab_resolve lut4_eval lut4_index ↻ sys_mmap ↻ fab_resolve ↻ rf_ncells ↻ enc

structs

none

consts

none

functions

22func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
25func enc(rd: i64, rs1: i64, rs2: i64, f3: i64, f7b5: i64) -> i64
30func ref_aluop(f3: i64, f7b5: i64) -> i64
42func cpu_exec(DI: *i64, DS: *i64, DP: *i64, AI: *i64, AS: *i64, AP: *i64, anpi: i64, CI: *i64, CS: *i64, CP: *i64, cnpi: i64, SI: *i64, SS: *i64, SP: *i64, snpi: i64, pi: *i64, co: *i64, ctrl: *i64, f3: i64, f7b5: i64, a: i64, b: i64) -> i64
50func main() -> i64