nx_fpga_pnr.nx

nx_fpga_pnr.nx -- LIB: sovereign PLACE-AND-ROUTE (omniforge SI M4, the nextpnr replacement) for the LUT4 fabric. Input = the nx_fpga_fabric bitstream netlist (ncells, npi, inits[], src[4*ncells]; a source s is PI s if s<npi else the output of cell s-npi). P&R does what fab_eval's implicit "index order" does NOT: (1) PLACE each cell on a DISTINCT 2D grid site, honoring topological columns -- every driver sits in a strictly-earlier column than its sink, so signals flow left->right with no combinational loop. (2) ROUTE every wire (PI->cell and cell->cell) as a shortest Manhattan path via Lee/BFS over a grid whose EDGES carry a finite channel capacity -- so routing CONGESTS and can FAIL. Routing success is capacity-gated, never fabricated. P&R preserves logic, so fab_eval over the (routed) driver map reproduces the golden function; the gate proves faithfulness + that routing is load-bearing (corrupt a net -> diverge) + that capacity exhaustion -> UNROUTABLE. never-brick #26: pure memory, BFS bounded by W*H nodes, deterministic, ZERO hardware writes. license_tier: ORIGINAL