code wiki / _hdl_build / nx_fpga_verilog_gate.nx

nx_fpga_verilog_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_verilog_gate.nx

10639 B174 linesdepth 5pulls 7 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 5 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_adder.nx nx_fpga_fabric.nx nx_syscalls.nx nx_fpga_verilog_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_adder.nxnx_fpga_fabric.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

structs

none

consts

none

functions

19func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
21func isdig(c: i64) -> i64 { if c < 48 { return 0 } if c > 57 { return 0 } return 1 }
24func wr_str(buf: *u8, off: i64, s: *u8) -> i64 { var o: i64=off; var i: i64=0; while s[i]!=(0 as u8){ buf[o]=s[i]; o=o+1; i=i+1 } return o }
called by 2: wr_operandfab_emit_verilog calls 1: sys_mmap
25func wr_int(buf: *u8, off: i64, v: i64) -> i64
34func wr_operand(buf: *u8, off: i64, s: i64, npi: i64) -> i64 { // pi[x] or n[x] (cell = s-npi)
42func fab_emit_verilog(buf: *u8, ncells: i64, npi: i64, npo: i64, inits: *i64, src: *i64, po: *i64) -> i64
72func rd_int(buf: *u8, pp: *i64) -> i64
called by 1: fab_parse
81func find_marker(buf: *u8, len: i64, from: i64, marker: *u8, mlen: i64) -> i64
92func fab_parse(buf: *u8, len: i64, rinits: *i64, rsrc: *i64, rpo: *i64, pnpi: *i64, pnpo: *i64) -> i64
114func run_adder(W: i64, ncells: i64, npi: i64, inits: *i64, src: *i64, po: *i64, a: i64, b: i64) -> i64
124func main() -> i64