code wiki / _hdl_build / nx_fpga_alu_verilog_gate.nx

nx_fpga_alu_verilog_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_alu_verilog_gate.nx

6438 B83 linesdepth 7pulls 12 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 6 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_verilog.nx nx_fpga_alu.nx rv64im_min_alu.nx nx_syscalls.nx nx_fpga_alu_verilog_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_verilog.nxnx_fpga_alu.nxrv64im_min_alu.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap fab_build_alu fl_gate_to_lut4 fl_gate_ref lut4_index fab_parity3_init fab_maj3_init fab_emit_verilog_seq vlg_wr_str vlg_wr_int sys_mmap ↻ vlg_wr_op vlg_wr_str ↻ vlg_wr_int ↻ gn fab_alu_run fab_eval fab_resolve lut4_eval lut4_index ↻ fab_po fab_resolve ↻ nx_rv64im_alu_compute nx_rv64im_lshr nx_rv64im_ltu nx_rv64im_sext32 nx_rv64im_mulh_signed nx_rv64im_mulh_unsigned nx_rv64im_lshr ↻ nx_rv64im_mulh_signed_unsi nx_rv64im_mulh_unsigned ↻ nx_rv64im_mulh_unsigned ↻ nx_rv64im_udiv nx_rv64im_ltu ↻ nx_rv64im_urem nx_rv64im_udiv ↻ sys_exit

structs

none

consts

none

functions

17func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
20func main() -> i64