code wiki / _hdl_build / nx_fpga_verilog_seq_gate.nx

nx_fpga_verilog_seq_gate.nx

buildroot/runtime/_hdl_build/nx_fpga_verilog_seq_gate.nx

5853 B88 linesdepth 5pulls 8 transitivereach 0 importersview sourcekind gate/prooftopic fpga
docsdependenciesstructsconstsfunctions

dependencies 6 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_fpga_verilog.nx nx_fpga_seq.nx nx_fpga_fabric.nx nx_syscalls.nx nx_fpga_verilog_seq_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_fpga_verilog.nxnx_fpga_seq.nxnx_fpga_fabric.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap seq_build_counter fl_gate_to_lut4 fl_gate_ref lut4_index fab_emit_verilog_seq vlg_wr_str vlg_wr_int sys_mmap ↻ vlg_wr_op vlg_wr_str ↻ vlg_wr_int ↻ gn run_counter sys_mmap ↻ seq_eval fab_resolve lut4_eval lut4_index ↻ fab_po fab_resolve ↻ seq_tick seq_eval ↻ sys_mmap ↻ fab_resolve ↻ sys_exit

structs

none

consts

none

functions

17func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
21func run_counter(W: i64, ncells: i64, npi: i64, kind: *i64, init: *i64, src: *i64, po: *i64, steps: i64, out: *i64) -> i64
37func main() -> i64