code wiki / _hdl_build / nx_nhdl_gate.nx

nx_nhdl_gate.nx

buildroot/runtime/_hdl_build/nx_nhdl_gate.nx

7761 B123 linesdepth 8pulls 17 transitivereach 0 importersview sourcekind gate/prooftopic nhdl
docsdependenciesstructsconstsfunctions

dependencies 9 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_nhdl.nx nx_fpga_rexec.nx nx_fpga_verilog.nx nx_fpga_seq.nx nx_fpga_fabric.nx rv64im_min_alu.nx nx_syscalls.nx nx_nhdl_gate.nx

imports: nx_gate_gn.nxnx_gate_base.nxnx_nhdl.nxnx_fpga_rexec.nxnx_fpga_verilog.nxnx_fpga_seq.nxnx_fpga_fabric.nxrv64im_min_alu.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap fab_build_rexec_alu sys_mmap ↻ fab_build_decode r9_sub r9_msel0 r9_msel1 r9_right r9_arith r9_uns r9_class sys_mmap ↻ fab_append fab_sub_out fab_build_alu fl_gate_to_lut4 fl_gate_ref lut4_index fab_parity3_init fab_maj3_init nhdl_emit nh_ws nh_wi sys_mmap ↻ nhdl_parse sys_mmap ↻ nh_skip_word nh_skip_ws nh_isws nh_isws ↻ nh_rd_int nh_skip_ws ↻ nh_isdig nh_skip_ws ↻ ref_aop fab_rexec_run fab_eval

structs

none

consts

none

functions

20func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
23func ref_aop(f3: i64, f7b5: i64) -> i64
30func main() -> i64