code wiki / _hdl_build / nx_nhdl_hier.nx

nx_nhdl_hier.nx

buildroot/runtime/_hdl_build/nx_nhdl_hier.nx

4961 B98 linesdepth 5pulls 6 transitivereach 2 importersview sourcekind librarytopic nhdl
docsdependenciesstructsconstsfunctions

about

nx_nhdl_hier.nx -- LIB: NHDL H2 -- HIERARCHY for the sovereign netlist format: a module DEFINED ONCE and INSTANTIATED many times (the "folded" netlist the researched 'Netlist' entry describes: "5 definitions -> 128 instances -> a million cells" -- compact reuse, the thing a flat netlist or a Verilog cell-dump can't do). GRAMMAR (v2): .nhdl 2 .def <name> <npi> <npo> <ncells> # a reusable module definition (local net numbering) L .. / D .. # its cells .po <local nets> .enddef .top <npi> <npo> # the top module .inst <name> <innet0> .. <innet{npi-1}> # instantiate <name>, wiring its PIs to top nets (PI / prior-inst output) ... .po <top nets> .end ELABORATION (unfolding) -> a single flat fabric, via the PROVEN fab_append (R32a): each .inst appends the module's cells with an inmap from its listed inputs; the instance's outputs become new top nets (tracked h2c[]). The flat result runs on fab_eval and round-trips through H1. NEVER-BRICK (#26): pure memory, bounded, deterministic. license_tier: ORIGINAL

dependencies 4 imports · 2 importers

nx_nhdl.nx nx_fpga_compose.nx nx_fpga_fabric.nx nx_syscalls.nx nx_nhdl_hier.nx nx_nhdl_hier_gate.nx nx_nhdl_scorecard_gate.nx

imports: nx_nhdl.nxnx_fpga_compose.nxnx_fpga_fabric.nxnx_syscalls.nx

imported by: nx_nhdl_hier_gate.nxnx_nhdl_scorecard_gate.nx

structs

none

consts

25const K_MAGIC_2048: i64 = 2048
26const K_MAGIC_4096: i64 = 4096

functions

29func nh_emit_cells(buf: *u8, o: i64, ncells: i64, kind: *i64, init: *i64, src: *i64) -> i64
called by 2: emit_chainsc_emit_chain calls 2: nh_wsnh_wi
44func nh_parse_cells(buf: *u8, pp: *i64, len: i64, ncells: i64, kind: *i64, init: *i64, src: *i64) -> i64
58func nhdl_hier_elaborate(buf: *u8, len: i64, cinit: *i64, csrc: *i64, ckind: *i64, cpo: *i64, outnpi: *i64, outnpo: *i64) -> i64