code wiki / _hdl_build / nx_nhdl_scorecard_gate.nx

nx_nhdl_scorecard_gate.nx

buildroot/runtime/_hdl_build/nx_nhdl_scorecard_gate.nx

10040 B133 linesdepth 8pulls 19 transitivereach 0 importersview sourcekind gate/prooftopic nhdl
docsdependenciesstructsconstsfunctions

dependencies 12 imports · 0 importers

nx_gate_gn.nx nx_gate_base.nx nx_nhdl.nx nx_nhdl_hier.nx nx_nrtl.nx nx_nbit.nx nx_fpga_verilog.nx nx_fpga_rexec.nx nx_fpga_adder.nx nx_fpga_fabric.nx nx_nhdl_scorecard_gate.nx

diagram shows first 10 each side; +2 more imports, +0 more importers in the complete lists below.

imports: nx_gate_gn.nxnx_gate_base.nxnx_nhdl.nxnx_nhdl_hier.nxnx_nrtl.nxnx_nbit.nxnx_fpga_verilog.nxnx_fpga_rexec.nxnx_fpga_adder.nxnx_fpga_fabric.nxrv64im_min_alu.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main gw sys_write sys_mmap fab_build_rexec_alu sys_mmap ↻ fab_build_decode r9_sub r9_msel0 r9_msel1 r9_right r9_arith r9_uns r9_class sys_mmap ↻ fab_append fab_sub_out fab_build_alu fl_gate_to_lut4 fl_gate_ref lut4_index fab_parity3_init fab_maj3_init nrtl_synth sys_mmap ↻ nh_skip_word nh_skip_ws nh_isws nh_isws ↻ nh_rd_int nh_skip_ws ↻ nh_isdig nh_skip_ws ↻ nr_rdc nh_skip_ws ↻ fab_build_ripple_adder fab_parity3_init ↻ fab_maj3_init ↻ fab_append ↻ fab_sub_out ↻

structs

none

consts

none

functions

21func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw(" PASS " as *u8) } else { gw(" FAIL " as *u8) } gw(name); gw("
calls 1: gw
25func sc_emit_chain(hbuf: *u8, mi: *i64, ms: *i64, mpo: *i64, m_npi: i64, m_npo: i64, m_nc: i64, W: i64, K: i64) -> i64
46func main() -> i64