code wiki / _hdl_build / nx_nhdl_scorecard_gate.nx
`nx_nhdl_scorecard_gate.nx` source

↩ module page · 133 lines · 10040 B
1import "nx_gate_gn.nx"
2import "nx_gate_base.nx"
3// nx_nhdl_scorecard_gate.nx -- GATE for NHDL H6: the MEASURED benchmark SCORECARD (the formal head-to-head capstone).
4// Every number is LIVE-MEASURED in this gate (no hardcoded claims), and the verdict HONESTLY separates two tiers:
5//   * MEASURED head-to-head: axes where we emit BOTH our artifact AND the incumbent's (Verilog), and compare bytes.
6//   * SOVEREIGN-CAP (named ref): axes where we PROVE our capability correct in-sim but the incumbent (Yosys/nextpnr/
7//     prjtrellis) is a NAMED yardstick we do NOT run -> NOT claimed as a measured exceed (per no-wave-measured-exceed).
8// LIAR-KILL: a fabricated "Verilog beats NHDL" axis is REFUSED because the live measurement shows the opposite ->
9//   EXCEED requires a live head-to-head AND ours<incumbent. expect_exit: 0  license_tier: ORIGINAL
10import "nx_nhdl.nx"
11import "nx_nhdl_hier.nx"
12import "nx_nrtl.nx"
13import "nx_nbit.nx"
14import "nx_fpga_verilog.nx"
15import "nx_fpga_rexec.nx"
16import "nx_fpga_adder.nx"
17import "nx_fpga_fabric.nx"
18import "rv64im_min_alu.nx"
19import "nx_syscalls.nx"
20
21func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw("  PASS " as *u8) } else { gw("  FAIL " as *u8) } gw(name); gw("
22" as *u8); return ok }
23
24// local hierarchical adder-chain emit (one .def adder8 + K insts) -- keeps the hierarchy measurement LIVE
25func sc_emit_chain(hbuf: *u8, mi: *i64, ms: *i64, mpo: *i64, m_npi: i64, m_npo: i64, m_nc: i64, W: i64, K: i64) -> i64 {
  let TNPI: i64=(K+1)*W + 1; let ZERO: i64=(K+1)*W
  var o: i64=0
  o=nh_ws(hbuf,o,".nhdl 2\n.def adder8 \x00" as *u8); o=nh_wi(hbuf,o,m_npi); o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,m_npo); o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,m_nc); o=nh_ws(hbuf,o,"\n\x00" as *u8)
  let zk: *i64=sys_mmap(8*64) as *i64; var z: i64=0; while z<m_nc { zk[z]=0; z=z+1 }
  o=nh_emit_cells(hbuf, o, m_nc, zk, mi, ms)
  o=nh_ws(hbuf,o,".po\x00" as *u8); var j: i64=0; while j<m_npo { o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,mpo[j]); j=j+1 }
  o=nh_ws(hbuf,o,"\n.enddef\n.top \x00" as *u8); o=nh_wi(hbuf,o,TNPI); o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,W); o=nh_ws(hbuf,o,"\n\x00" as *u8)
  var i: i64=0
  while i<K {
      o=nh_ws(hbuf,o,".inst adder8\x00" as *u8)
      var b: i64=0; while b<W { var net: i64=b; if i>0 { net=TNPI+(i-1)*m_npo+b } o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,net); b=b+1 }
      b=0; while b<W { o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,(i+1)*W+b); b=b+1 }
      o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,ZERO); o=nh_ws(hbuf,o,"\n\x00" as *u8)
      i=i+1
  }
  o=nh_ws(hbuf,o,".po\x00" as *u8); var b2: i64=0; while b2<W { o=nh_ws(hbuf,o," \x00" as *u8); o=nh_wi(hbuf,o,TNPI+(K-1)*m_npo+b2); b2=b2+1 }
  o=nh_ws(hbuf,o,"\n.end\n\x00" as *u8)
  return o
44}
45
46func main() -> i64 {
  gw("=== nx_nhdl_scorecard: NHDL H6 -- MEASURED head-to-head scorecard (sovereign HDL/EDA vs incumbents) ===\n" as *u8)
  let W: i64=8
  var pass: i64=0; var total: i64=0
50
  // ---------- build real artifacts ----------
  // 584-cell RV64 CPU datapath (decode+ALU) for the format axis
  let ci_cpu: *i64=sys_mmap(8*700) as *i64; let cs_cpu: *i64=sys_mmap(8*2800) as *i64; let ck_cpu: *i64=sys_mmap(8*700) as *i64; let cp_cpu: *i64=sys_mmap(8*72) as *i64; let on_cpu: *i64=sys_mmap(16) as *i64
  let NC_cpu: i64=fab_build_rexec_alu(64, ci_cpu, cs_cpu, ck_cpu, cp_cpu, on_cpu); let NPI_cpu: i64=on_cpu[0]
  // synthesized RTL fabric (32 gates) for abstraction + P&R axes
  let srclit: *u8=".nrtl 1\n.module demo 8\n.in a b\n.out y\nt = a & b\nu = a ^ b\ny = t + u\n.end\n\x00" as *u8
  let mbuf: *u8=sys_mmap(4096); var rc: i64=0; while srclit[rc]!=(0 as u8){ mbuf[rc]=srclit[rc]; rc=rc+1 } mbuf[rc]=0 as u8
  let ci_r: *i64=sys_mmap(8*256) as *i64; let cs_r: *i64=sys_mmap(8*1024) as *i64; let ck_r: *i64=sys_mmap(8*256) as *i64; let cp_r: *i64=sys_mmap(8*32) as *i64
  let on_r: *i64=sys_mmap(16) as *i64; let op_r: *i64=sys_mmap(16) as *i64; let oW_r: *i64=sys_mmap(16) as *i64
  let cn_r: i64=nrtl_synth(mbuf, rc, ci_r, cs_r, ck_r, cp_r, on_r, op_r, oW_r); let NPI_r: i64=on_r[0]
  // hierarchical adder chain (K=4) for the folding axis
  let mi: *i64=sys_mmap(8*64) as *i64; let ms: *i64=sys_mmap(8*256) as *i64; let mpo: *i64=sys_mmap(8*16) as *i64
  let m_npi: i64=fab_build_ripple_adder(W, mi, ms, mpo)
  let hbuf: *u8=sys_mmap(16384); let hier_B: i64=sc_emit_chain(hbuf, mi, ms, mpo, m_npi, W+1, 2*W, W, 4)
  let ci_h: *i64=sys_mmap(8*256) as *i64; let cs_h: *i64=sys_mmap(8*1024) as *i64; let ck_h: *i64=sys_mmap(8*256) as *i64; let cp_h: *i64=sys_mmap(8*32) as *i64; let on_h: *i64=sys_mmap(16) as *i64; let op_h: *i64=sys_mmap(16) as *i64
  let cn_h: i64=nhdl_hier_elaborate(hbuf, hier_B, ci_h, cs_h, ck_h, cp_h, on_h, op_h)
67
  // ---------- LIVE measurements ----------
  let b1: *u8=sys_mmap(131072); let b2: *u8=sys_mmap(131072); let b3: *u8=sys_mmap(16384)
  let nhdl_A: i64=nhdl_emit(b1, "cpu" as *u8, NC_cpu, NPI_cpu, 64, ck_cpu, ci_cpu, cs_cpu, cp_cpu)     // our format
  let vlog_A: i64=fab_emit_verilog_seq(b2, NC_cpu, NPI_cpu, 64, ck_cpu, ci_cpu, cs_cpu, cp_cpu)        // Verilog
  let flat_B: i64=nhdl_emit(b3, "flat" as *u8, cn_h, on_h[0], W, ck_h, ci_h, cs_h, cp_h)               // flattened
  let rtl_C: i64=rc                                                                                     // RTL source bytes
  let vlog_C: i64=fab_emit_verilog_seq(b1, cn_r, NPI_r, W, ck_r, ci_r, cs_r, cp_r)                      // Verilog of the synth
75
  // synthesis correctness (vs Yosys, named): synth fabric == oracle
  let pi: *i64=sys_mmap(8*128) as *i64; let co: *i64=sys_mmap(8*256) as *i64
  var seed: i64=20260626; var synth_ok: i64=1; var sc1: i64=0
  while sc1<50 {
      seed=(seed*1103515245+12345)&2147483647; let a: i64=seed&255
      seed=(seed*1103515245+12345)&2147483647; let bb: i64=seed&255
      var bit: i64=0; while bit<W { pi[bit]=(a>>bit)&1; pi[W+bit]=(bb>>bit)&1; bit=bit+1 } pi[2*W]=0
      fab_eval(cn_r, NPI_r, ci_r, cs_r, pi, co)
      var s: i64=0; bit=0; while bit<W { let v: i64=fab_resolve(cp_r[bit], NPI_r, pi, co); s=s|(v<<bit); bit=bit+1 }
      if s != (((a&bb)+(a^bb))&255) { synth_ok=0 }
      sc1=sc1+1
  }
  // P&R correctness (vs nextpnr/prjtrellis, named): place + virtual FPGA == oracle
  let tile_of: *i64=sys_mmap(8*64) as *i64; nbit_place(cn_r, 6, 6, tile_of)
  let tileval: *i64=sys_mmap(8*64) as *i64; let out: *i64=sys_mmap(8*32) as *i64
  var pnr_ok: i64=1; var sc2: i64=0
  while sc2<50 {
      seed=(seed*1103515245+12345)&2147483647; let a: i64=seed&255
      seed=(seed*1103515245+12345)&2147483647; let bb: i64=seed&255
      var bit: i64=0; while bit<W { pi[bit]=(a>>bit)&1; pi[W+bit]=(bb>>bit)&1; bit=bit+1 } pi[2*W]=0
      nbit_eval(cn_r, NPI_r, W, tile_of, ci_r, cs_r, cp_r, pi, tileval, out)
      var s: i64=0; bit=0; while bit<W { s=s|((out[bit]&1)<<bit); bit=bit+1 }
      if s != (((a&bb)+(a^bb))&255) { pnr_ok=0 }
      sc2=sc2+1
  }
101
  // ---------- SCORECARD ----------
  gw("\n  AXIS                     OURS      INCUMBENT   TIER                              VERDICT\n" as *u8)
  gw("  FORMAT (584-cell CPU)    " as *u8); gn(nhdl_A); gw("B     " as *u8); gn(vlog_A); gw("B     MEASURED vs Verilog            " as *u8)
  if nhdl_A<vlog_A { gw("EXCEED (" as *u8); gn(vlog_A/nhdl_A); gw("x smaller)\n" as *u8) } else { gw("no\n" as *u8) }
  gw("  HIERARCHY (folding)      " as *u8); gn(hier_B); gw("B      " as *u8); gn(flat_B); gw("B      MEASURED vs flat netlist        " as *u8)
  if hier_B<flat_B { gw("EXCEED (" as *u8); gn(flat_B*10/hier_B); gw("/10x)\n" as *u8) } else { gw("no\n" as *u8) }
  gw("  RTL ABSTRACTION          " as *u8); gn(rtl_C); gw("B       " as *u8); gn(vlog_C); gw("B     MEASURED vs Verilog-gates        " as *u8)
  if rtl_C<vlog_C { gw("EXCEED (" as *u8); gn(vlog_C/rtl_C); gw("x denser)\n" as *u8) } else { gw("no\n" as *u8) }
  gw("  SYNTHESIS (RTL->gates)   proven    [Yosys]     SOVEREIGN-CAP vs NAMED ref         " as *u8)
  if synth_ok==1 { gw("CORRECT (not a measured exceed)\n" as *u8) } else { gw("FAIL\n" as *u8) }
  gw("  PLACE&ROUTE+BITSTREAM    proven    [nextpnr]   SOVEREIGN-CAP vs NAMED ref         " as *u8)
  if pnr_ok==1 { gw("CORRECT (not a measured exceed)\n" as *u8) } else { gw("FAIL\n" as *u8) }
114
  // ---------- VERDICT + LIAR-KILL ----------
  var mexc: i64=0
  if nhdl_A<vlog_A { mexc=mexc+1 }
  if hier_B<flat_B { mexc=mexc+1 }
  if rtl_C<vlog_C { mexc=mexc+1 }
  let neg_exceed: i64=0   // fabricated "Verilog<NHDL" claim
  var nf: i64=0; if vlog_A<nhdl_A { nf=1 }
  gw("\n  measured head-to-head EXCEEDs=" as *u8); gn(mexc); gw("/3   sovereign capabilities proven=" as *u8); gn(synth_ok+pnr_ok); gw("/2\n" as *u8)
  // T1: all 3 measured axes are live EXCEEDs
  total=total+1; if mexc==3 { pass=pass+1; gw("  [PASS] T1 all 3 measured axes are LIVE head-to-head wins vs Verilog\n" as *u8) } else { gw("  [FAIL] T1\n" as *u8) }
  // T2: both sovereign capabilities correctness-proven (NOT claimed as measured exceeds)
  total=total+1; if synth_ok==1 { if pnr_ok==1 { pass=pass+1; gw("  [PASS] T2 synthesis + P&R proven CORRECT in-sim vs named refs (honestly NOT counted as measured exceeds)\n" as *u8) } else { gw("  [FAIL] T2\n" as *u8) } } else { gw("  [FAIL] T2\n" as *u8) }
  // T3 LIAR-KILL: the fabricated reverse claim is refused by the live measurement
  total=total+1; if nf==0 { pass=pass+1; gw("  [PASS] T3 LIAR-KILL: fabricated 'Verilog<NHDL' REFUSED -- EXCEED requires a live head-to-head AND ours<incumbent\n" as *u8) } else { gw("  [FAIL] T3\n" as *u8) }
129
  gw("SCORECARD verdict=" as *u8)
  if pass==total { gw("GREEN passes=" as *u8); gn(pass); gw("/" as *u8); gn(total); gw(" (3 measured exceeds + 2 sovereign caps proven; honest tiers)\n" as *u8); sys_exit(0); return 0 }
  gw("RED passes=" as *u8); gn(pass); gw("/" as *u8); gn(total); gw("\n" as *u8); sys_exit(1); return 1
133}
nx_nhdl_scorecard_gate.nx source

`nx_nhdl_scorecard_gate.nx` source
