nx_nrtl_opt.nx

nx_nrtl_opt.nx -- LIB: NHDL logic-OPTIMIZATION pass (closes the QoR-behind axis). The synthesizer (H4) lowers RTL to gates directly = correct but UNOPTIMIZED (the scorecard's one honest 'BEHIND' vs Yosys). This is the missing optimizer: two general, equivalence-preserving netlist transforms measured by GATE-COUNT REDUCTION (the metric logic-opt is judged on -- cited knowledge/library/eda_logicopt.txt: "cost = literal count, correlates with area"): * CSE (common-subexpression elimination): cells with identical (kind, init, canonicalized-srcs) compute the same value -> merge duplicates, redirect references. * DCE (dead-cell elimination): cells not in the transitive fanin of any primary output are removed. Both are SAFE BY CONSTRUCTION (they never change any output) -> the optimized netlist == the original, fewer gates. NEVER-BRICK (#26): pure memory, bounded, deterministic. license_tier: ORIGINAL