code wiki / _hdl_build / nx_nxgate_sim_test.nx
nx_nxgate_sim_test.nx
buildroot/runtime/_hdl_build/nx_nxgate_sim_test.nx
about
nx_nxgate_sim_test.nx -- proof-of-life GATE for the gate-level functional
simulator (VERIFIER organ's hardware oracle, SIL-3).
Builds a small word-level netlist by hand and proves:
(1) the simulator EVALUATES combinational cells correctly (XOR/ADD/SUB/MUL/
EQ/MUX) over an input vector;
(2) it CATCHES the SIL-1 stub class: a DIV represented as an ADD cell (what
the ALU gate emitter actually emits today) DIVERGES from behavioral DIV
-- the divergence the verifier exists to surface.
Vector a=12 b=4. Known answer (FAIL LOUD): "8 16 8 48 0 16 16 3 " =
xor add sub mul eq mux divstub realdiv. (divstub=16 != realdiv=3 -> caught)
dependencies 1 imports · 0 importers
imports: nx_nxgate_sim.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 16 | func _emit_num(v: i64) -> i64 called by 1: main |
| 24 | func _nl() -> i64 { let z: *u8 = sys_mmap(2); z[0] = 10; sys_write(1, z, 1); return 0 } called by 1: main |
| 26 | func main() -> i64 |