code wiki / _hdl_build / nx_gsim_seq_test.nx
nx_gsim_seq_test.nx
buildroot/runtime/_hdl_build/nx_gsim_seq_test.nx
about
nx_gsim_seq_test.nx -- proves the SEQUENTIAL gate simulator (nx_gsim_tick): a
netlist with DFFs that holds + updates STATE across clocked ticks. This is the
keystone that makes a gate-level CPU RUNNABLE (registers, PC, accumulators).
Two stateful elements share the clock:
Q1 (counter): D1 = Q1 + 1 -> Q1 counts ticks
Q2 (accumulator): D2 = Q2 + in -> Q2 sums the per-tick inputs
Drive in=[10,20,30] then 97 idle ticks (in=0). After 100 ticks: Q1=100, Q2=60.
Known answer: "100 60", exit 0.
dependencies 1 imports · 0 importers
imports: nx_nxgate_sim.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 13 | func _set(c: *NxGsimCell, id: i64, kind: i64, fo: i64, f0: i64, f1: i64, val: i64) -> i64 called by 1: main |
| 17 | func _emit_dec(v: i64) -> i64 called by 1: main |
| 25 | func _nl() -> i64 { let z: *u8 = sys_mmap(2); z[0] = 10; sys_write(1, z, 1); return 0 } called by 1: main |
| 27 | func main() -> i64 |