nx_alu_netlist_test.nx

nx_alu_netlist_test.nx -- VERIFIER on the REAL ALU op-select topology (SIL-3 closure, layer-7). Builds a 3-op (ADD/SUB/DIV) ALU netlist using the EXACT structure the .nxgate ALU emitter (synth_emit_alu_gates.nx) emits: per op a CONST(opcode) + a binop subnet + an EQ(op_in==opcode) match, then a cascade MUX(match, this, prev). DIV is emitted as an ADD cell -- the SIL-1 stub (emitter lines 151-158, "TODO_SILICON proper divider"). Simulating over op_in proves: the correct ops (ADD/SUB) match the behavioral ALU, and DIV (= a+b stub) DIVERGES from behavioral a/b -- the verifier CATCHES the silent gate-emit miscompile via op-selection (what structural-only smokes miss). a=20 b=4. Known answer (FAIL LOUD): "24 24 16 16 24 5 " = res_add beh_add res_sub beh_sub res_div beh_div. (res_div=24 != beh=5 -> caught)