nx_compute_ladder.nx source
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1// nx_compute_ladder.nx -- GENEALOGIST physics grade for COMPUTE (the AI/research-engine foundation).
2// Unlike storage reads (at the memory floor), compute is the BIGGEST suspected gap to physics. The
3// physics ceiling for f32 compute = the silicon's peak FLOP/s = cores x freq x (SIMD lanes x FMA). This
4// MEASURES the sovereign hardware-float GEMM throughput, reads THIS CPU's cores+freq live from /proc/cpuinfo,
5// derives the f32 peak at each capability level (scalar / SSE-packed / AVX2-FMA / all-cores), and grades the
6// matmul on ABSENT->EXISTS->EXCEEDS->NEAR-PHYSICS->PHYSICS-OPTIMUM -- quantifying exactly how far from the
7// silicon limit, and which LOCKED levers (packed SIMD / FMA / multicore / blocking) close it.
8// Honest: the matmul is CORRECT (bit-exact, proven elsewhere) but single-thread scalar-SSE today.
9// No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
10import "nx_f32_hw.nx"
11import "nx_syscalls.nx"
12const K_MAGIC_2880: i64 = 2880
13
14func cl_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
15func cl_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 }
16
17// inlined hardware-float GEMM (same kernel as nx_f32_hw_matmul; that organ has a main() so we can't import it)
18func cl_matmul(a: *i64, b: *i64, c: *i64, m: i64, k: i64, n: i64) -> i64 {
19 var i: i64=0
20 while i<m { var j: i64=0; while j<n { var acc: i64=__f32_from_i64(0); var l: i64=0; while l<k { acc=__f32_add(acc, __f32_mul(a[i*k+l], b[l*n+j])); l=l+1 } c[i*n+j]=acc; j=j+1 } i=i+1 }
21 return 0
22}
23// count logical cores = occurrences of "processor" at line starts in cpuinfo
24func cl_cores(buf: *u8, len: i64) -> i64 {
25 var c: i64=0
26 var i: i64=0
27 while i<len-9 { if buf[i]==(112 as u8) { if buf[i+1]==(114 as u8) { if buf[i+2]==(111 as u8) { if buf[i+3]==(99 as u8) { if buf[i+4]==(101 as u8) { if buf[i+5]==(115 as u8) { if buf[i+6]==(115 as u8) { if buf[i+7]==(111 as u8) { if buf[i+8]==(114 as u8) { c=c+1 } } } } } } } } } i=i+1 }
28 return c
29}
30// parse the first "MHz" integer value from cpuinfo
31func cl_mhz(buf: *u8, len: i64) -> i64 {
32 var i: i64=0
33 var result: i64=0
34 var found: i64=0
35 while i<len-3 {
36 if found==0 { if buf[i]==(77 as u8) { if buf[i+1]==(72 as u8) { if buf[i+2]==(122 as u8) {
37 var j: i64=i+3
38 var go: i64=1
39 while go==1 { if j>=len { go=0 } else { if buf[j]==(58 as u8) { go=0 } else { j=j+1 } } }
40 j=j+1
41 while buf[j]==(32 as u8) { j=j+1 }
42 var v: i64=0
43 var pg: i64=1
44 while pg==1 { let ch: i64=buf[j] as i64; if ch>=48 { if ch<=57 { v=v*10+(ch-48); j=j+1 } else { pg=0 } } else { pg=0 } }
45 result=v; found=1
46 } } } }
47 i=i+1
48 }
49 return result
50}
51
52func main() -> i64 {
53 cl_puts("GENEALOGIST physics grade: sovereign f32 COMPUTE (matmul) vs the silicon FLOP ceiling\n" as *u8)
54
55 // --- measure the sovereign hw-float matmul throughput ---
56 let SZ: i64=128
57 let A: *i64=sys_mmap(SZ*SZ*8); let B: *i64=sys_mmap(SZ*SZ*8); let C: *i64=sys_mmap(SZ*SZ*8)
58 var i: i64=0
59 while i<SZ*SZ { A[i]=f32_of((i%7)+1); B[i]=f32_of((i%5)+1); i=i+1 }
60 let reps: i64=3
61 let t0: i64=sys_now_us()
62 var r: i64=0
63 while r<reps { cl_matmul(A, B, C, SZ, SZ, SZ); r=r+1 }
64 let t1: i64=sys_now_us()
65 var us: i64=t1-t0
66 if us<=0 { us=1 }
67 let flop: i64 = 2*SZ*SZ*SZ*reps
68 let mflops: i64 = flop/us // FLOP per microsecond == MFLOP/s
69
70 // --- read THIS CPU + derive the f32 physics peak ---
71 let lenp: *i64=sys_mmap(8) as *i64
72 let info: *u8=sys_read_file("/proc/cpuinfo\x00" as *u8, lenp)
73 var cores: i64=1
74 var mhz: i64=K_MAGIC_2880
75 if (info as i64)!=0 { cores=cl_cores(info, lenp[0]); mhz=cl_mhz(info, lenp[0]); if cores<=0 { cores=1 } if mhz<=0 { mhz=K_MAGIC_2880 } }
76 let scalar_1c: i64 = mhz*2 // MFLOP/s: 2 FLOP/cycle scalar f32
77 let sse_1c: i64 = scalar_1c*4 // 4-wide packed SSE
78 let avxfma_1c: i64 = scalar_1c*16 // 8-wide AVX2 x 2(FMA)
79 let peak_all: i64 = avxfma_1c*cores // all cores
80
81 cl_puts(" CPU: "); cl_num(cores); cl_puts(" cores @ "); cl_num(mhz); cl_puts(" MHz\n" as *u8)
82 cl_puts(" SOVEREIGN matmul = "); cl_num(mflops); cl_puts(" MFLOP/s (single-thread scalar-SSE, bit-exact)\n" as *u8)
83 cl_puts(" f32 PHYSICS CEILING (derived): scalar-1core="); cl_num(scalar_1c); cl_puts(" SSE-1core="); cl_num(sse_1c); cl_puts(" AVX2FMA-1core="); cl_num(avxfma_1c); cl_puts(" ALL-CORES="); cl_num(peak_all); cl_puts(" MFLOP/s\n\n" as *u8)
84
85 let gap_scalar: i64 = scalar_1c/mflops
86 let gap_peak: i64 = peak_all/mflops
87 cl_puts(" MATURITY LADDER:\n" as *u8)
88 cl_puts(" exists + bit-exact correct? YES (proven vs software f32 differential)\n" as *u8)
89 cl_puts(" vs 1-core SCALAR f32 ceiling ~"); cl_num(gap_scalar); cl_puts("x below (loop overhead, no blocking)\n" as *u8)
90 cl_puts(" vs FULL silicon f32 peak ~"); cl_num(gap_peak); cl_puts("x below = FAR from PHYSICS-OPTIMUM\n" as *u8)
91 cl_puts(" grade: EXISTS -- the BIGGEST gap to physics in the stack (storage reads are AT the floor; compute is ~"); cl_num(gap_peak); cl_puts("x away)\n" as *u8)
92 cl_puts(" LEVERS to the floor (the LOCKED axes): packed SIMD (~4-8x) -> FMA (~2x) -> multicore (~"); cl_num(cores); cl_puts("x) -> cache blocking (~2-4x)\n\n" as *u8)
93
94 var pass: i64=0
95 var ttl: i64=0
96 ttl=ttl+1; cl_puts(" T1 sovereign matmul measured (>0 MFLOP/s): " as *u8); if mflops>0 { pass=pass+1; cl_puts("PASS\n" as *u8) } else { cl_puts("FAIL\n" as *u8) }
97 ttl=ttl+1; cl_puts(" T2 CPU read live (cores>1, MHz>0): " as *u8); if cores>1 { if mhz>0 { pass=pass+1; cl_puts("PASS\n" as *u8) } else { cl_puts("FAIL\n" as *u8) } } else { cl_puts("FAIL\n" as *u8) }
98 ttl=ttl+1; cl_puts(" T3 physics ceiling derived + gap quantified (>0): " as *u8); if gap_peak>0 { pass=pass+1; cl_puts("PASS\n" as *u8) } else { cl_puts("FAIL\n" as *u8) }
99 ttl=ttl+1; cl_puts(" T4 HONEST: compute is FAR from physics (gap >= 10x) -- not overclaimed as optimal: " as *u8); if gap_peak>=10 { pass=pass+1; cl_puts("PASS\n" as *u8) } else { cl_puts("(unexpectedly near floor)\n" as *u8) }
100
101 cl_puts("NX-COMPUTE-LADDER passed "); cl_num(pass); cl_puts("/"); cl_num(ttl)
102 if pass>=3 { cl_puts(" verdict=GREEN (compute graded vs the silicon FLOP ceiling -- the gap + levers quantified honestly)\n" as *u8); sys_exit(0); return 0 }
103 cl_puts(" verdict=RED\n" as *u8); sys_exit(1); return 1
104}