nx_compute_ladder.nx
buildroot/runtime/nx_compute_ladder.nx
about
nx_compute_ladder.nx -- GENEALOGIST physics grade for COMPUTE (the AI/research-engine foundation).
Unlike storage reads (at the memory floor), compute is the BIGGEST suspected gap to physics. The
physics ceiling for f32 compute = the silicon's peak FLOP/s = cores x freq x (SIMD lanes x FMA). This
MEASURES the sovereign hardware-float GEMM throughput, reads THIS CPU's cores+freq live from /proc/cpuinfo,
derives the f32 peak at each capability level (scalar / SSE-packed / AVX2-FMA / all-cores), and grades the
matmul on ABSENT->EXISTS->EXCEEDS->NEAR-PHYSICS->PHYSICS-OPTIMUM -- quantifying exactly how far from the
silicon limit, and which LOCKED levers (packed SIMD / FMA / multicore / blocking) close it.
Honest: the matmul is CORRECT (bit-exact, proven elsewhere) but single-thread scalar-SSE today.
No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_f32_hw.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 12 | const K_MAGIC_2880: i64 = 2880 |
functions
| 14 | func cl_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 15 | func cl_num(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } |
| 18 | func cl_matmul(a: *i64, b: *i64, c: *i64, m: i64, k: i64, n: i64) -> i64 called by 1: main |
| 24 | func cl_cores(buf: *u8, len: i64) -> i64 called by 1: main |
| 31 | func cl_mhz(buf: *u8, len: i64) -> i64 called by 1: main |
| 52 | func main() -> i64 |