nx_crypto_hw_limit_map.nx source
↩ module page · 44 lines · 4142 B
1// nx_crypto_hw_limit_map.nx -- THE literal-hardware answer: per crypto rung, is the speed gap a PHYSICS limit (silicon
2// LACKS the instruction) or a DESIGN limit (silicon HAS it, nx_cc doesn't EMIT it)? Reads crypto_rung_hw_limits.conf
3// (specific instructions named + verified vs the CPU generation that introduced them). Operator 2026-07-02: "know EXACTLY
4// ... specifics not opinion." Loosely-coupled sibling of nx_crypto_sclass_rung_census. license_tier: ORIGINAL
5import "nx_syscalls.nx"
6
7func gw(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
8func gn(v: i64) -> i64 { if v==0 { sys_write(1,"0" as *u8,1); return 0 } var m: i64=v; let t: *u8=sys_mmap(24); var k: i64=0; while m>0 { t[k]=(48+(m%10)) as u8; m=m/10; k=k+1 } let o: *u8=sys_mmap(24); var w: i64=0; var q: i64=k-1; while q>=0 { o[w]=t[q]; w=w+1; q=q-1 } sys_write(1,o,w); return 0 }
9func cf(src: *u8, cur: i64, n: i64, out: *u8) -> i64 {
10 var i: i64=cur; var k: i64=0
11 while i<n { let c: i64=src[i] as i64; if c==124 { out[k]=0 as u8; return i+1 } if c==10 { out[k]=0 as u8; return i } out[k]=src[i]; k=k+1; i=i+1 }
12 out[k]=0 as u8; return i
13}
14
15func main() -> i64 {
16 gw("=== nx_crypto_hw_limit_map: PHYSICS (silicon lacks it) vs DESIGN (silicon has it, we don't emit it)? -- specifics ===\n\n" as *u8)
17 let lb: *i64 = sys_mmap(8) as *i64
18 let buf: *u8 = sys_read_file("knowledge/registry/crypto_rung_hw_limits.conf" as *u8, lb)
19 if buf==0 as *u8 { gw("no conf\n" as *u8); sys_exit(1); return 1 }
20 let n: i64 = lb[0]
21 let f0: *u8=sys_mmap(48); let f1: *u8=sys_mmap(48); let f2: *u8=sys_mmap(48); let f3: *u8=sys_mmap(160)
22 let f4: *u8=sys_mmap(64); let f5: *u8=sys_mmap(64); let f6: *u8=sys_mmap(200)
23 var design: i64=0; var physics: i64=0; var rungs: i64=0
24 var cur: i64=0
25 while cur<n {
26 var eol: i64=cur; var g: i64=1
27 while g==1 { if eol>=n { g=0 } else { if buf[eol]==(10 as u8) { g=0 } else { eol=eol+1 } } }
28 if eol>cur { if buf[cur]!=(35 as u8) {
29 var c: i64=cur
30 c=cf(buf,c,eol,f0); c=cf(buf,c,eol,f1); c=cf(buf,c,eol,f2); c=cf(buf,c,eol,f3); c=cf(buf,c,eol,f4); c=cf(buf,c,eol,f5); c=cf(buf,c,eol,f6)
31 rungs=rungs+1
32 gw(" [" as *u8); gw(f0); gw("] " as *u8); gw(f1); gw(" gap=" as *u8); gw(f2); gw("\n" as *u8)
33 gw(" SOTA-HW: " as *u8); gw(f3); gw(" (since " as *u8); gw(f4); gw(")\n" as *u8)
34 if f5[0]==(68 as u8) { gw(" >>> DESIGN limit -- the silicon HAS the instruction; nx_cc does NOT emit it. FIXABLE.\n" as *u8); design=design+1 } else { gw(" >>> PHYSICS limit -- silicon lacks it (algorithmic race).\n" as *u8); physics=physics+1 }
35 gw(" class=" as *u8); gw(f5); gw(" FIX=" as *u8); gw(f6); gw("\n\n" as *u8)
36 } }
37 cur=eol+1
38 }
39 gw("=== HW-limit map: " as *u8); gn(rungs); gw(" rungs -- DESIGN(fixable, silicon has it)=" as *u8); gn(design); gw(" PHYSICS(on modern x86)=" as *u8); gn(physics); gw(" ===\n" as *u8)
40 gw("ANSWER (specific, not opinion): on any >=2013 x86, ALL " as *u8); gn(design); gw(" gaps are DESIGN -- the silicon ALREADY HAS the instruction (AES-NI 2010, MULX/ADX/AVX2 2013-14, SHA-NI 2016); nx_cc/nxasm_x86 does NOT emit it. The limit is OUR COMPILER BACKEND, not physics. We CAN reach SOTA speed by emitting the named instructions -- we would run the IDENTICAL silicon path OpenSSL uses -- while sovereignty+proven-correctness+16-ISA-portability stay the exceed.\n" as *u8)
41 gw("PHYSICS applies ONLY on silicon LACKING an instruction (pre-2010 no-AES-NI, pre-2016 no-SHA-NI, no-AVX2 embedded) -- there NOBODY has HW accel, so it is a pure algorithmic-design race (still winnable by better design, just no free HW for anyone incl OpenSSL).\n" as *u8)
42 gw("BUILD PATH (hardware rung up, lowest first, each = additive instruction-encoding in nxasm + an intrinsic + KAT-gated): R1/R2 MULX+ADCX+ADOX (bignum/field) -> R2 comb-table+Montgomery (pure algo) -> R3 AESENC+PCLMULQDQ (AES-GCM) -> R3 SHA256RNDS2 -> R3 AVX2 ChaCha. Then per-ISA (NEON crypto ext on ARM, etc).\n" as *u8)
43 sys_exit(0); return 0
44}