nx_crypto_hw_limit_map.nx
buildroot/runtime/nx_crypto_hw_limit_map.nx
about
nx_crypto_hw_limit_map.nx -- THE literal-hardware answer: per crypto rung, is the speed gap a PHYSICS limit (silicon
LACKS the instruction) or a DESIGN limit (silicon HAS it, nx_cc doesn't EMIT it)? Reads crypto_rung_hw_limits.conf
(specific instructions named + verified vs the CPU generation that introduced them). Operator 2026-07-02: "know EXACTLY
... specifics not opinion." Loosely-coupled sibling of nx_crypto_sclass_rung_census. license_tier: ORIGINAL
dependencies 1 imports · 0 importers
imports: nx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 7 | func gw(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 8 | func gn(v: i64) -> i64 { if v==0 { sys_write(1,"0" as *u8,1); return 0 } var m: i64=v; let t: *u8=sys_mmap(24); var k: i64=0; while m>0 { t[k]=(48+(m%10)) as u8; m=m/10; k=k+1 } let o: *u8=sys_mmap(24); var w: i64=0; var q: i64=k-1; while q>=0 { o[w]=t[q]; w=w+1; q=q-1 } sys_write(1,o,w); return 0 } |
| 9 | func cf(src: *u8, cur: i64, n: i64, out: *u8) -> i64 called by 1: main |
| 15 | func main() -> i64 |