nx_ctxsw_emit.nx source

1// nx_ctxsw_emit.nx -- CONTEXT SWITCH between two address spaces (satp swap, X-PAGE-CTXSW-001). The 2// essence of multiprocess virtual memory: two DISTINCT page tables map the SAME virtual address 3// (0xC0009000) to DIFFERENT physical pages; swapping satp between them makes one VA read each process's 4// own memory. Needs 4KB-page leaves (X-PAGE-4K-001) since a gigapage can't distinguish PAs within RAM. 5// 6// Table A @0x80001000 (ppn .1/.2/.3 -> data @0x80004000 sentinel 0x0A0A1111); 7// Table B @0x80005000 (ppn .5/.6/.7 -> data @0x80008000 sentinel 0x0B0B2222). Both carry the identity 8// code-map (root[VPN2=2]) so the S-mode code stays fetchable across the swap. Sequence (S-mode): 9// load VA 0xC0009000 (satp=A) -> sentinel_A ; csrrw satp=B (CONTEXT SWITCH) ; load SAME VA -> sentinel_B 10// -> verify A!=B and each matches -> "CSW". 11// satp2_ppn (argv[1]) -- the 2nd satp's root ppn. default 0x80005 = table B (real switch -> CSW). The 12// gate's control passes 0x80001 = table A (NO switch) -> same VA reads the same 13// value -> CSW never prints, proving the swap is load-bearing. 14// out-path (argv[2]). 15// Sovereign, no gcc/.sh. license_tier: ORIGINAL 16import "nx_syscalls.nx" 17const CS_MAGIC_8192: i64 = 8192 18 19const CS_OUT: *u8 = "runtime/_hdl_build/_ctxsw_virt.bin" 20const CS_GOLD: *u8 = "runtime/_hdl_build/_ctxsw_virt.bin.gold" 21const CS_LOG: *u8 = "knowledge/status/priv.log" 22 23const CS_UART: i64 = 0x10000000 24const CS_FIN: i64 = 0x100000 25const CS_PASS: i64 = 0x5555 26const CS_MEM_BASE: i64 = 0x80000000 27const CS_CSR_SATP: i64 = 0x180 28const CS_CSR_MSTATUS: i64 = 0x300 29const CS_CSR_MEPC: i64 = 0x341 30const CS_MRET: i64 = 0x30200073 31const CS_MPP_S: i64 = 0x800 32 33const RV_X0: i64 = 0 34const RV_T0: i64 = 5 35const RV_T1: i64 = 6 36const RV_T2: i64 = 7 37const RV_T3: i64 = 28 38const RV_T4: i64 = 29 39const RV_T5: i64 = 30 40 41const CS_VA: i64 = 0xC0009000 // VPN2=3, VPN1=0, VPN0=9 -> 4KB leaf in each table 42const CS_TBLA: i64 = 0x80001000 // table A root (ppn 0x80001) 43const CS_TBLB: i64 = 0x80005000 // table B root (ppn 0x80005) 44const CS_SENT_A: i64 = 0x0A0A1111 // bit31 clear (lw sign-extends to a positive that li32 matches) 45const CS_SENT_B: i64 = 0x0B0B2222 46const CS_SV39: i64 = 8 47const CS_SATP_A_PPN: i64 = 0x80001 48 49func cs_lui(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37 } 50func cs_addi(rd: i64, rs1: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13 } 51func cs_load(rd: i64, rs1: i64, f3: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x03 } 52func cs_store(rs2: i64, rs1: i64, f3: i64, imm: i64) -> i64 { 53 let hi: i64 = ((imm >> 5) & 0x7f) << 25 54 let lo: i64 = (imm & 0x1f) << 7 55 return hi | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | lo | 0x23 56} 57func cs_branch(rs1: i64, rs2: i64, f3: i64, imm: i64) -> i64 { 58 let b12: i64 = ((imm >> 12) & 0x1) << 31 59 let b11: i64 = ((imm >> 11) & 0x1) << 7 60 let b10_5: i64 = ((imm >> 5) & 0x3f) << 25 61 let b4_1: i64 = ((imm >> 1) & 0xf) << 8 62 return b12 | b10_5 | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | b4_1 | b11 | 0x63 63} 64func cs_jal(rd: i64, imm: i64) -> i64 { 65 let b20: i64 = ((imm >> 20) & 0x1) << 31 66 let b19_12: i64 = ((imm >> 12) & 0xff) << 12 67 let b11: i64 = ((imm >> 11) & 0x1) << 20 68 let b10_1: i64 = ((imm >> 1) & 0x3ff) << 21 69 return b20 | b10_1 | b11 | b19_12 | (rd << 7) | 0x6f 70} 71func cs_slli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x13 } 72func cs_srli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (5 << 12) | (rd << 7) | 0x13 } 73func cs_or(rd: i64, rs1: i64, rs2: i64) -> i64 { return (rs2 << 20) | (rs1 << 15) | (6 << 12) | (rd << 7) | 0x33 } 74func cs_csrrw(rd: i64, csr: i64, rs1: i64) -> i64 { return ((csr & 0xfff) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x73 } 75func cs_w32(buf: *u8, off: i64, w: i64) -> i64 { buf[off]=(w&0xff) as u8; buf[off+1]=((w>>8)&0xff) as u8; buf[off+2]=((w>>16)&0xff) as u8; buf[off+3]=((w>>24)&0xff) as u8; return off+4 } 76func cs_li32(buf: *u8, off: i64, rd: i64, val: i64) -> i64 { 77 var hi: i64 = (val >> 12) & 0xFFFFF 78 var lo: i64 = val & 0xFFF 79 if lo >= 0x800 { lo = lo - 0x1000; hi = (hi + 1) & 0xFFFFF } 80 var o: i64 = cs_w32(buf, off, cs_lui(rd, hi)) 81 o = cs_w32(buf, o, cs_addi(rd, rd, lo)) 82 return o 83} 84func cs_li32u(buf: *u8, off: i64, rd: i64, val: i64) -> i64 { 85 var o: i64 = cs_li32(buf, off, rd, val) 86 o = cs_w32(buf, o, cs_slli(rd, rd, 32)) 87 o = cs_w32(buf, o, cs_srli(rd, rd, 32)) 88 return o 89} 90func cs_emit_str(buf: *u8, off: i64, s: *u8, n: i64) -> i64 { 91 var o: i64 = off 92 var i: i64 = 0 93 while i < n { o = cs_w32(buf, o, cs_addi(RV_T1, RV_X0, s[i] as i64)); o = cs_w32(buf, o, cs_store(RV_T1, RV_T0, 0, 0)); i = i + 1 } 94 return o 95} 96func cs_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 97func cs_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } 98 99// emit the instruction sequence that lays one 3-level table (4KB leaf for VA 0xC0009000) + its sentinel. 100// root@root_base, L1@+0x1000, L0@+0x2000, data@+0x3000; ppns root_ppn .. +3. Returns new offset. 101func cs_lay_table(buf: *u8, off: i64, root_base: i64, sentinel: i64) -> i64 { 102 var o: i64 = off 103 let root_ppn: i64 = root_base >> 12 104 let root3: i64 = ((root_ppn + 1) << 10) | 1 // root[VPN2=3] non-leaf -> L1 105 let l1pte: i64 = ((root_ppn + 2) << 10) | 1 // L1[0] non-leaf -> L0 106 let l0pte: i64 = ((root_ppn + 3) << 10) | 7 // L0[9] 4KB leaf -> data (V|R|W) 107 o = cs_li32u(buf, o, RV_T5, root_base) 108 o = cs_li32(buf, o, RV_T1, 0x2000000F); o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0x10)) // root[2] identity code gigapage 109 o = cs_li32(buf, o, RV_T1, root3); o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0x18)) // root[3] -> L1 110 o = cs_li32u(buf, o, RV_T5, root_base + 0x1000) 111 o = cs_li32(buf, o, RV_T1, l1pte); o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0)) // L1[0] -> L0 112 o = cs_li32u(buf, o, RV_T5, root_base + 0x2000) 113 o = cs_li32(buf, o, RV_T1, l0pte); o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0x48)) // L0[9] leaf -> data 114 o = cs_li32u(buf, o, RV_T5, root_base + 0x3000) 115 o = cs_li32(buf, o, RV_T1, sentinel); o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0)) // sentinel in the data page 116 return o 117} 118 119// emit: build satp = (Sv39<<60) | ppn into t1 and csrrw it. Uses t1,t2. 120func cs_set_satp(buf: *u8, off: i64, ppn: i64) -> i64 { 121 var o: i64 = off 122 o = cs_li32(buf, o, RV_T1, ppn) 123 o = cs_w32(buf, o, cs_addi(RV_T2, RV_X0, CS_SV39)) 124 o = cs_w32(buf, o, cs_slli(RV_T2, RV_T2, 60)) 125 o = cs_w32(buf, o, cs_or(RV_T1, RV_T1, RV_T2)) 126 o = cs_w32(buf, o, cs_csrrw(RV_X0, CS_CSR_SATP, RV_T1)) 127 return o 128} 129 130// pos_out[0]=CONT (S-mode), [1]=FAIL, [2]=HALT 131func cs_emit_image(buf: *u8, cont_off: i64, fail_off: i64, halt_off: i64, pos_out: *i64, satp2_ppn: i64) -> i64 { 132 var o: i64 = 0 133 o = cs_w32(buf, o, cs_lui(RV_T0, CS_UART >> 12)) // t0 = UART 134 o = cs_lay_table(buf, o, CS_TBLA, CS_SENT_A) // build process A's page table 135 o = cs_lay_table(buf, o, CS_TBLB, CS_SENT_B) // build process B's page table 136 o = cs_set_satp(buf, o, CS_SATP_A_PPN) // satp = table A 137 o = cs_li32u(buf, o, RV_T1, CS_MEM_BASE + cont_off) // mepc = &cont ; enter S-mode 138 o = cs_w32(buf, o, cs_csrrw(RV_X0, CS_CSR_MEPC, RV_T1)) 139 o = cs_li32(buf, o, RV_T1, CS_MPP_S) 140 o = cs_w32(buf, o, cs_csrrw(RV_X0, CS_CSR_MSTATUS, RV_T1)) 141 o = cs_w32(buf, o, CS_MRET) 142 pos_out[0] = o // CONT (S-mode) 143 o = cs_li32u(buf, o, RV_T5, CS_VA) // load VA via table A 144 o = cs_w32(buf, o, cs_load(RV_T3, RV_T5, 2, 0)) // t3 = sentinel_A 145 o = cs_set_satp(buf, o, satp2_ppn) // *** CONTEXT SWITCH *** (default table B) 146 o = cs_li32u(buf, o, RV_T5, CS_VA) // load the SAME VA via the 2nd table 147 o = cs_w32(buf, o, cs_load(RV_T4, RV_T5, 2, 0)) // t4 = sentinel of the 2nd address space 148 o = cs_li32(buf, o, RV_T1, CS_SENT_A) 149 let pcb1: i64 = o 150 o = cs_w32(buf, o, cs_branch(RV_T3, RV_T1, 1, fail_off - pcb1)) // t3 must be sentinel_A (read via A) 151 o = cs_li32(buf, o, RV_T1, CS_SENT_B) 152 let pcb2: i64 = o 153 o = cs_w32(buf, o, cs_branch(RV_T4, RV_T1, 1, fail_off - pcb2)) // t4 must be sentinel_B (read via B after the swap) 154 o = cs_emit_str(buf, o, "CSW" as *u8, 3) // same VA, two different PAs across the satp swap 155 o = cs_w32(buf, o, cs_jal(RV_X0, halt_off - o)) 156 pos_out[1] = o // FAIL (swap did not change the mapping) 157 o = cs_emit_str(buf, o, "CX" as *u8, 2) 158 pos_out[2] = o // HALT 159 o = cs_li32(buf, o, RV_T5, CS_FIN) 160 o = cs_li32(buf, o, RV_T1, CS_PASS) 161 o = cs_w32(buf, o, cs_store(RV_T1, RV_T5, 2, 0)) 162 o = cs_w32(buf, o, cs_jal(RV_X0, 0)) 163 return o 164} 165 166func cs_parse_num(s: *u8) -> i64 { 167 var q: i64 = 0; var val: i64 = 0 168 if s[0] == (48 as u8) { if s[1] == (120 as u8) { 169 q = 2 170 var go: i64 = 1 171 while go == 1 { let c: i64 = s[q] as i64; var d: i64 = 0-1; if c>=48 { if c<=57 { d=c-48 } } if c>=97 { if c<=102 { d=c-87 } } if c>=65 { if c<=70 { d=c-55 } } if d<0 { go=0 } else { val=val*16+d; q=q+1 } } 172 return val 173 }} 174 var go2: i64 = 1 175 while go2 == 1 { let c: i64 = s[q] as i64; if c>=48 { if c<=57 { val=val*10+(c-48); q=q+1 } else { go2=0 } } else { go2=0 } } 176 return val 177} 178 179func main(argc: i64, argv: *i64) -> i64 { 180 var satp2_ppn: i64 = 0x80005 // default: switch to table B 181 var outp: *u8 = CS_OUT 182 if argc >= 2 { satp2_ppn = cs_parse_num(argv[1] as *u8) } 183 if argc >= 3 { outp = argv[2] as *u8 } 184 let scratch: *u8 = sys_mmap(CS_MAGIC_8192) 185 let pos: *i64 = sys_mmap(32) as *i64 186 cs_emit_image(scratch, 0, 0, 0, pos, satp2_ppn) 187 let cont_off: i64 = pos[0] 188 let fail_off: i64 = pos[1] 189 let halt_off: i64 = pos[2] 190 let buf: *u8 = sys_mmap(CS_MAGIC_8192) 191 let sz: i64 = cs_emit_image(buf, cont_off, fail_off, halt_off, pos, satp2_ppn) 192 let fd: i64 = sys_openat_wr(outp, 420) 193 if fd < 0 { cs_p("CTXSWEMIT verdict=RED reason=out-unwritable\n" as *u8); return 1 } 194 sys_write(fd, buf, sz); sys_close(fd) 195 let gold: *u8 = sys_mmap(8) 196 gold[0]=67 as u8; gold[1]=83 as u8; gold[2]=87 as u8 // "CSW" 197 let gfd: i64 = sys_openat_wr(CS_GOLD, 420) 198 if gfd >= 0 { sys_write(gfd, gold, 3); sys_close(gfd) } 199 cs_p("CTXSWEMIT name=" as *u8); cs_p(outp); cs_p(" bytes=" as *u8); cs_fn(1, sz); cs_p(" (satp-swap context switch, same VA -> 2 address spaces)\n" as *u8) 200 let lf: i64 = sys_openat_append(CS_LOG, 420) 201 if lf >= 0 { var n: i64=0; let m: *u8="CTXSWEMIT authored _ctxsw_virt.bin golden=CSW\n" as *u8; while m[n]!=(0 as u8){n=n+1} sys_write(lf,m,n); sys_close(lf) } 202 return 0 203}