code wiki / _hdl_build / nx_ctxsw_emit.nx

nx_ctxsw_emit.nx

buildroot/runtime/_hdl_build/nx_ctxsw_emit.nx

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about

nx_ctxsw_emit.nx -- CONTEXT SWITCH between two address spaces (satp swap, X-PAGE-CTXSW-001). The essence of multiprocess virtual memory: two DISTINCT page tables map the SAME virtual address (0xC0009000) to DIFFERENT physical pages; swapping satp between them makes one VA read each process's own memory. Needs 4KB-page leaves (X-PAGE-4K-001) since a gigapage can't distinguish PAs within RAM. Table A @0x80001000 (ppn .1/.2/.3 -> data @0x80004000 sentinel 0x0A0A1111); Table B @0x80005000 (ppn .5/.6/.7 -> data @0x80008000 sentinel 0x0B0B2222). Both carry the identity code-map (root[VPN2=2]) so the S-mode code stays fetchable across the swap. Sequence (S-mode): load VA 0xC0009000 (satp=A) -> sentinel_A ; csrrw satp=B (CONTEXT SWITCH) ; load SAME VA -> sentinel_B -> verify A!=B and each matches -> "CSW". satp2_ppn (argv[1]) -- the 2nd satp's root ppn. default 0x80005 = table B (real switch -> CSW). The gate's control passes 0x80001 = table A (NO switch) -> same VA reads the same value -> CSW never prints, proving the swap is load-bearing. out-path (argv[2]). Sovereign, no gcc/.sh. license_tier: ORIGINAL

dependencies 1 imports · 0 importers

nx_syscalls.nx nx_ctxsw_emit.nx

imports: nx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main cs_parse_num sys_mmap cs_emit_image cs_w32 cs_lui cs_lay_table cs_li32u cs_li32 cs_w32 ↻ cs_lui ↻ cs_addi cs_w32 ↻ cs_slli cs_srli cs_li32 ↻ cs_w32 ↻ cs_store cs_set_satp cs_li32 ↻ cs_w32 ↻ cs_addi ↻ cs_slli ↻ cs_or cs_csrrw cs_li32u ↻ cs_csrrw ↻ cs_li32 ↻ cs_load cs_branch cs_emit_str cs_w32 ↻ cs_addi ↻ cs_store ↻ cs_jal cs_store ↻ sys_openat_wr cs_p sys_write sys_write ↻

structs

none

consts

17const CS_MAGIC_8192: i64 = 8192
19const CS_OUT: *u8 = "runtime/_hdl_build/_ctxsw_virt.bin"
20const CS_GOLD: *u8 = "runtime/_hdl_build/_ctxsw_virt.bin.gold"
21const CS_LOG: *u8 = "knowledge/status/priv.log"
23const CS_UART: i64 = 0x10000000
24const CS_FIN: i64 = 0x100000
25const CS_PASS: i64 = 0x5555
26const CS_MEM_BASE: i64 = 0x80000000
27const CS_CSR_SATP: i64 = 0x180
28const CS_CSR_MSTATUS: i64 = 0x300
29const CS_CSR_MEPC: i64 = 0x341
30const CS_MRET: i64 = 0x30200073
31const CS_MPP_S: i64 = 0x800
33const RV_X0: i64 = 0
34const RV_T0: i64 = 5
35const RV_T1: i64 = 6
36const RV_T2: i64 = 7
37const RV_T3: i64 = 28
38const RV_T4: i64 = 29
39const RV_T5: i64 = 30
41const CS_VA: i64 = 0xC0009000 // VPN2=3, VPN1=0, VPN0=9 -> 4KB leaf in each table
42const CS_TBLA: i64 = 0x80001000 // table A root (ppn 0x80001)
43const CS_TBLB: i64 = 0x80005000 // table B root (ppn 0x80005)
44const CS_SENT_A: i64 = 0x0A0A1111 // bit31 clear (lw sign-extends to a positive that li32 matches)
45const CS_SENT_B: i64 = 0x0B0B2222
46const CS_SV39: i64 = 8
47const CS_SATP_A_PPN: i64 = 0x80001

functions

49func cs_lui(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37 }
50func cs_addi(rd: i64, rs1: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13 }
51func cs_load(rd: i64, rs1: i64, f3: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x03 }
called by 1: cs_emit_image
52func cs_store(rs2: i64, rs1: i64, f3: i64, imm: i64) -> i64
57func cs_branch(rs1: i64, rs2: i64, f3: i64, imm: i64) -> i64
called by 1: cs_emit_image
64func cs_jal(rd: i64, imm: i64) -> i64
called by 1: cs_emit_image
71func cs_slli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x13 }
called by 2: cs_li32ucs_set_satp
72func cs_srli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (5 << 12) | (rd << 7) | 0x13 }
called by 1: cs_li32u
73func cs_or(rd: i64, rs1: i64, rs2: i64) -> i64 { return (rs2 << 20) | (rs1 << 15) | (6 << 12) | (rd << 7) | 0x33 }
called by 1: cs_set_satp
74func cs_csrrw(rd: i64, csr: i64, rs1: i64) -> i64 { return ((csr & 0xfff) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x73 }
75func cs_w32(buf: *u8, off: i64, w: i64) -> i64 { buf[off]=(w&0xff) as u8; buf[off+1]=((w>>8)&0xff) as u8; buf[off+2]=((w>>16)&0xff) as u8; buf[off+3]=((w>>24)&0xff) as u8; return off+4 }
76func cs_li32(buf: *u8, off: i64, rd: i64, val: i64) -> i64
84func cs_li32u(buf: *u8, off: i64, rd: i64, val: i64) -> i64
90func cs_emit_str(buf: *u8, off: i64, s: *u8, n: i64) -> i64
called by 1: cs_emit_image calls 3: cs_w32cs_addics_store
96func cs_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
called by 1: main calls 1: sys_write
97func cs_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 }
called by 1: main calls 2: sys_mmapsys_write
101func cs_lay_table(buf: *u8, off: i64, root_base: i64, sentinel: i64) -> i64
120func cs_set_satp(buf: *u8, off: i64, ppn: i64) -> i64
131func cs_emit_image(buf: *u8, cont_off: i64, fail_off: i64, halt_off: i64, pos_out: *i64, satp2_ppn: i64) -> i64
166func cs_parse_num(s: *u8) -> i64
called by 1: main
179func main(argc: i64, argv: *i64) -> i64