code wiki / _hdl_build / nx_f64_exp_register.nx
`nx_f64_exp_register.nx` source

1// nx_f64_exp_register.nx -- registers ME1 rung 1 (binary64 exp) via the Librarian
2// (cl_next_idx allocation + dual-write).  ENGINEER evidence = BOTH gates re-run here:
3// the f64 core regression gate (cvt grew to_i64/ldexp this rung) AND the exp ULP gate.
4// license_tier: ORIGINAL
5import "nx_cap_register.nx"
6import "nx_capreg_librarian.nx"
7import "nx_syscalls.nx"
8
9func f6er_run(path: *u8) -> i64 {
10    let pid: i64 = sys_fork()
11    if pid == 0 {
12        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
13        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
14        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
15        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
16        sys_execve(path, argv, envp); sys_exit(127)
17    }
18    let st: *i64 = sys_mmap(16) as *i64
19    sys_wait4(pid, st, 0)
20    return st[0]
21}
22
23func main() -> i64 {
24    var allok: i64 = 1
25    if f6er_run("/tmp/_f64_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
26    if f6er_run("/tmp/_f64_exp_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
27    cr_w(1, "ENGINEER: f64 core regression + exp ULP gates pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
28    let eng: i64 = ig_engineer(1, 1, 1, allok)
29    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
30    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
31    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
32    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
33    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
34    let idx: i64 = cl_next_idx(lp, jp)
35    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
36        2, "GEN F64-EXP ULP1 (ME1 rung 1, DLMF ch.4 opens) -- binary64 exp bits-up: Cody-Waite ln2 split (25-bit hi, k*hi EXACT) + degree-15 Horner + ldexp gradual underflow; ALL constants GENERATED from mpmath@60dps runtime (_f64_exp_consts.nx, zero hand-derived); plus nx_f64_to_i64/nx_f64_ldexp in cvt. GATE _f64_exp_gate_authored: 203 correctly-rounded oracle vectors -> exact=190 ulp1=13 worse=0 MAX-ULP=1 (bound MEASURED not asserted), tamper-tested RED@i=5->GREEN; f64 core regression 1217/1217 held. THE TEMPLATE for the transcendental family + the MATH_KERNEL pattern emitter (range-reduce/poly/ULP-gate shape); next: log/sin/cos/atan/pow then DLMF ch.5 gamma. Composes CAPREG265" as *u8)
37    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
38    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED (ME1 exp, max-ulp=1)\n" as *u8)
39    sys_exit(0)
40    return 0
41}
nx_f64_exp_register.nx source

`nx_f64_exp_register.nx` source
