code wiki / _hdl_build / nx_fpga_census.nx
`nx_fpga_census.nx` source

↩ module page · 110 lines · 20987 B
1// nx_fpga_census.nx -- the FPGA-BOOT-SIM capability census as a code-defined seed into the SOVEREIGN seg-store
2// (knowledge/store/fpgacen-*, via nx_seg_store). Operator: "use the nishi ecosystem." The 9 rungs (R4-R10a) were
3// tracked only in Claude memory; this records them in the ecosystem's OWN sovereign storage + census machinery
4// (the nx_reader_census pattern: author-by-organ, idempotent, byte-verified -- NO TSV), AND GATE-BACKS the claim:
5// it forks the REAL R9 milestone gate live (must be GREEN) plus a neg-control bogus gate (must be non-zero) so the
6// census cannot fabricate a PRESENT it can't reproduce. Each cell names its proving gate; ALL 9 ran GREEN this
7// session. expect_exit: 0  license_tier: ORIGINAL
8import "nx_fpga_census_store.nx"   // FC_PREFIX / fc_seg_next_p / fc_streq_store
9import "nx_seg_store.nx"           // ss_begin / ss_add / ss_commit
10import "nx_syscalls.nx"
11
12const FCEN_RUNNER: *u8 = "_offc/nx_sov_build_run.elf"
13
14func cw(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
15func cn(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{sys_write(1,"-\x00" as *u8,1);m=0-m} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1} sys_write(1,bb,k); return 0 }
16func clen(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} return n }
17
18// fork+exec the sovereign runner on a gate name; /dev/null stdio; return WEXITSTATUS (gate verdict).
19func fc_run_gate(name: *u8) -> i64 {
  let pid: i64 = sys_fork()
  if pid == 0 {
      let dn: i64 = sys_openat_wr("/dev/null\x00" as *u8, 420)
      if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
      let argv: *i64 = sys_mmap(64) as *i64
      argv[0] = FCEN_RUNNER as i64; argv[1] = name as i64; argv[2] = 0
      let envp: *i64 = sys_mmap(16) as *i64
      envp[0] = "PATH=/usr/bin:/bin\x00" as *u8 as i64; envp[1] = 0
      sys_execve(FCEN_RUNNER, argv, envp)
      sys_exit(127)
  }
  let st: *i64 = sys_mmap(16) as *i64
  sys_wait4(pid, st, 0)
  return (st[0] >> 8) & 0xff
34}
35
36func main() -> i64 {
  cw("=== nx_fpga_census: FPGA-boot-sim capability ladder -> sovereign seg-store (knowledge/store/fpgacen-, NO TSV) ===\n" as *u8)
  let keys: *i64 = sys_mmap(8 * 48) as *i64
  let vals: *i64 = sys_mmap(8 * 48) as *i64
40
  keys[0]="fc:ids" as *u8 as i64; vals[0]="FC01\tFC02\tFC03\tFC04\tFC05\tFC06\tFC07\tFC08\tFC09\tFC10\tFC11\tFC12\tFC13\tFC14\tFC15\tFC16\tFC17\tFC18\tFC19\tFC20\tFC21\tFC22\tFC23\tFC24\tFC25\tFC26\tFC27\tFC28\tFC29\tFC30\tFC31" as *u8 as i64
  keys[1]="fc:FC01" as *u8 as i64; vals[1]="FC01\tR4\tFPGA fabric primitive LUT4 + gate->LUT4 tech-map\tECP5 LUT4 (Lattice)\tPRESENT-in-sim\tnx_fpga_lut_gate\tevery gate primitive compiles to one LUT4 bitstream, 128 exhaustive checks" as *u8 as i64
  keys[2]="fc:FC02" as *u8 as i64; vals[2]="FC02\tR5\tbitstream-configured fabric EXECUTES real circuits (LUT cells + routing)\tnextpnr/prjtrellis fabric\tPRESENT-in-sim\tnx_fpga_fabric_gate\tfull-adder + routed chain run from the bitstream alone, exhaustive" as *u8 as i64
  keys[3]="fc:FC03" as *u8 as i64; vals[3]="FC03\tR6\twide ADD tech-mapped to a LUT4 network (ripple-carry)\tyosys HDL synthesis\tPRESENT-in-sim\tnx_fpga_adder_gate\tW=1/4 exhaustive + W to 32 == native add, 792 checks" as *u8 as i64
  keys[4]="fc:FC04" as *u8 as i64; vals[4]="FC04\tR7\top-selected ADD/SUB ALU unit (two's-complement)\tCPU ALU\tPRESENT-in-sim\tnx_fpga_addsub_gate\tsubtraction + op-selection on the fabric == native" as *u8 as i64
  keys[5]="fc:FC05" as *u8 as i64; vals[5]="FC05\tR8\tlogic+arith ALU == BEHAVIORAL ALU @64-bit\tnx_rv64im_alu_compute (team CPU ALU)\tPRESENT-in-sim\tnx_fpga_alu_gate\tAND/OR/XOR/ADD/SUB == behavioral, 1050 checks 0 mismatch" as *u8 as i64
  keys[6]="fc:FC06" as *u8 as i64; vals[6]="FC06\tR8b\tcompares SLT/SLTU from subtractor carry/sign == behavioral\tnx_rv64im_alu_compute\tPRESENT-in-sim\tnx_fpga_cmp_gate\tsigned-overflow-correct + unsigned-borrow, 309 checks each" as *u8 as i64
  keys[7]="fc:FC07" as *u8 as i64; vals[7]="FC07\tR8c\tbarrel shifter SLL/SRL/SRA (log-depth) == behavioral\tnx_rv64im_alu_compute\tPRESENT-in-sim\tnx_fpga_shift_gate\tall 64 shamts + arithmetic sign-fill, 324 checks/op" as *u8 as i64
  keys[8]="fc:FC08" as *u8 as i64; vals[8]="FC08\tR9\tR-TYPE INSTRUCTION decode+execute on the fabric == behavioral CPU\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_rtype_gate\tdecoder fabric + datapath == behavioral, all 10 ops, 1280 checks" as *u8 as i64
  keys[9]="fc:FC09" as *u8 as i64; vals[9]="FC09\tR10a\tSEQUENTIAL fabric: DFF state + clock tick -> a program counter\tFPGA DFF / CPU regfile+PC\tPRESENT-in-sim\tnx_fpga_counter_gate\tclocked counter holds+increments, full 2^8 cycle + wraparound" as *u8 as i64
  keys[10]="fc:FC10" as *u8 as i64; vals[10]="FC10\tR10\tREGISTER FILE on the sequential fabric (addressed clocked write + addressed read, x0=0)\tCPU register file\tPRESENT-in-sim\tnx_fpga_regfile_gate\tR registers x W DFFs + LUT4 address-decode + clock-edge write + x0 hardwired 0; R=4/8 round-trip + hold + clock-edge + liar-kill" as *u8 as i64
  keys[11]="fc:FC11" as *u8 as i64; vals[11]="FC11\tR11\ta RUNNING CPU: multi-instruction R-type program decode+execute+writeback on the fabric == behavioral CPU step-for-step\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu_gate\tfabric regfile(R10)+decode/execute(R9) compose a per-instr step; 6-instr program incl data-dependency == reference, 48 register-compares 0 mismatch, liar-killed" as *u8 as i64
  keys[12]="fc:FC12" as *u8 as i64; vals[12]="FC12\tR12\tSELF-CONTAINED program (R-type + I-TYPE immediates) runs on the fabric CPU, no pre-load == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu2_gate\tADDI bootstrap + sign-extended immediates + operand-B mux; reuses R9 datapaths; 8-instr program == reference 64 register-compares 0 mismatch, liar-killed" as *u8 as i64
  keys[13]="fc:FC13" as *u8 as i64; vals[13]="FC13\tR13\tCONTROL FLOW: a LOOP with branches runs on the fabric (PC as a loadable fabric register + B-type branches, condition on the fabric) == behavioral step-for-step\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu3_gate\tnx_fpga_pc loadable PC register (incr-or-load) + BNE/BEQ/BLT.. ; sum(1..3)=6 loop, PC+regfile == reference 117 compares 0 mismatch, liar-killed" as *u8 as i64
  keys[14]="fc:FC14" as *u8 as i64; vals[14]="FC14\tR14\tMEMORY: LOADS/STORES (LW/SW) + a data-memory fabric; a store->load roundtrip program == behavioral (regfile + memory)\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu4_gate\tdata memory = the regfile fabric with a 2nd state array; load/store address computed on the fabric ALU; SW 100->mem[3]/200->mem[5] then LW back + ADD=300, regfile+memory == reference 112 compares 0 mismatch, liar-killed" as *u8 as i64
  keys[15]="fc:FC15" as *u8 as i64; vals[15]="FC15\tR15\tJUMPS JAL/JALR: function calls on the fabric CPU (link rd<-PC+1 + PC<-target) == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu5_gate\tJAL link+jump, JALR return (rs1+imm on the fabric ALU); a call->compute->return program, PC+regfile == reference 72 compares 0 mismatch, liar-killed" as *u8 as i64
  keys[16]="fc:FC16" as *u8 as i64; vals[16]="FC16\tR16\tthe UNIFIED RV64I CPU: ONE step handles R/I/B/load/store/jump and runs ONE real program using them ALL == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu6_gate\tstore a 3-elem array to memory, JAL to a sum function that LOOPS (BNE) LOADING each element + accumulating, JALR return, caller reads result=60; regfile+memory+PC == reference 510 compares over 30 steps 0 mismatch, liar-killed" as *u8 as i64
  keys[17]="fc:FC17" as *u8 as i64; vals[17]="FC17\tR17\ta true RAM fabric: every address (INCLUDING address 0) is writable and reads back what was written -- a memory, not a register file (which hardwires x0->0)\tSRAM/BRAM block\tPRESENT-in-sim\tnx_fpga_ram_gate\tseq_build_ram = the regfile structure with a D-feed MUX on ALL R words (no x0 hardwire); 8 distinct words to addr 0..7 read back exact, addr 0 held nonzero + re-writable, liar-killed" as *u8 as i64
  keys[18]="fc:FC18" as *u8 as i64; vals[18]="FC18\tR18\tINSTRUCTION FETCH FROM A MEMORY FABRIC (von Neumann): the CPU reads each instruction from the IMEM RAM fabric at the PC, then decodes+executes == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu7_gate\tprogram loaded INTO the IMEM fabric; instr=ram_read(IMEM,PC) each step -> decode/ALU/regfile/PC; x3=12 x4=24 == reference, fetch-integrity all 4 == loaded, liar-kill: corrupt IMEM word 2 -> CPU executes the changed instruction (x3=1)" as *u8 as i64
  keys[19]="fc:FC19" as *u8 as i64; vals[19]="FC19\tR19\tthe UNIFIED von Neumann CPU: ONE machine FETCHES code from an IMEM RAM fabric AND stores/loads data in a DMEM RAM fabric (incl ADDRESS 0) == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu8_gate\tintegrates R16(unified)+R17(true RAM)+R18(fetch); program stores a 2-elem array to DMEM starting at addr 0, loads both back, sums=30; regfile+DMEM == reference 112 compares 0 mismatch; liar-kill: NOP the store-to-addr-0 -> sum=20 (result depends on memory)" as *u8 as i64
  keys[20]="fc:FC20" as *u8 as i64; vals[20]="FC20\tR20\tCONTROL FLOW on the von Neumann machine: a real LOOP fetched from IMEM, branch (BNE) target into the fabric PC + condition on the fabric ALU, summing a DMEM array == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_cpu9_gate\tstore 3-elem array to DMEM from addr 0, LOOP (LW->ADD->index++->BNE while !=count) summing 10+20+30=60; loop-carried x4/x6/PC track reference every step + full regfile+DMEM == reference at end; liar-killed" as *u8 as i64
  keys[21]="fc:FC21" as *u8 as i64; vals[21]="FC21\tR21\tLUI + AUIPC (U-type upper-immediate) on the fabric ALU == behavioral -> the sim now covers EVERY RV64I register-writing op class {R,I,LOAD,STORE,BRANCH,JAL,JALR,LUI,AUIPC}\tnx_rv64im_alu_compute / RV64I U-type\tPRESENT-in-sim\tnx_fpga_lui_gate\tLUI rd=sign_extend32(imm<<12) over 8 values incl negative; AUIPC rd=PC+(imm<<12) over 40 (pc,imm) cases; both computed on the fabric ALU; liar-killed (corrupt ALU -> diverges)" as *u8 as i64
  keys[22]="fc:FC22" as *u8 as i64; vals[22]="FC22\tR22\ta SELF-LOADING BOOTLOADER on a UNIFIED von Neumann memory: a loader/bootrom copies a payload image load->run region (LW/SW) in a single RAM fabric holding code+data, then JALR jumps and the CPU FETCHES+runs the loaded code == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_boot_gate\tunified MEM (16 words, code+data); loader at MEM[0..12] copies MEM[13]->MEM[14] then jumps; payload runs x6=42 from the COPIED slot; full boot == behavioral von Neumann 0 mismatch; T2 MEM[14]==MEM[13]; liar-killed" as *u8 as i64
  keys[23]="fc:FC23" as *u8 as i64; vals[23]="FC23\tR23\tSYSTEM/ECALL -- the TRAP primitive (syscall / kernel-entry control transfer): ECALL saves the return addr to mepc + traps to a handler vector, the handler runs + returns (JALR through mepc), the program uses the result == behavioral\trv64im_min_sim (team CPU)\tPRESENT-in-sim\tnx_fpga_ecall_gate\tprogram on the von Neumann machine ECALLs -> handler@vector sets x6=99 -> returns through mepc(x5=2) -> x3=100; == behavioral 0 mismatch; SIMPLIFIED (mepc=GP reg, fixed vector, no CSR/privilege); liar-killed" as *u8 as i64
  keys[24]="fc:FC24" as *u8 as i64; vals[24]="FC24\tR24\tMUL (M-extension) on the fabric via SEQUENTIAL SHIFT-ADD: for each set bit i of b, add (a<<i) to an accumulator -- shift on the fabric barrel shifter, add on the fabric ALU -- == behavioral MUL\tnx_rv64im_alu_compute(MUL)\tPRESENT-in-sim\tnx_fpga_mul_gate\ta*b low-64 via fabric shift-add over 12 (a,b) pairs (0/identity/powers-of-2/primes/all-ones/large-a) == oracle 0 mismatch incl 255*255=65025; multi-cycle multiplier style; liar-killed. HONEST: MUL only -- DIV/REM/MULH not yet" as *u8 as i64
  keys[25]="fc:FC25" as *u8 as i64; vals[25]="FC25\tR25\tDIVU/REMU (M-extension division) on the fabric via RESTORING DIVISION: per dividend bit, compare partial remainder to divisor (fabric SLTU) + conditionally SUBTRACT (fabric ALU) + set quotient bit -- == behavioral DIVU(quotient) AND REMU(remainder)\tnx_rv64im_alu_compute(DIVU/REMU)\tPRESENT-in-sim\tnx_fpga_div_gate\trestoring divider over 10 pairs both q+r == oracle 0 mismatch incl 100/7=14 rem 2; sequential divider style; liar-killed. WITH MUL (R24) -> the rv64iM INTEGER SET IS COMPLETE IN SIM. HONEST: unsigned DIVU/REMU (signed DIV/REM + b=0 special-case are the oracle's, follow-on)" as *u8 as i64
  keys[26]="fc:FC26" as *u8 as i64; vals[26]="FC26\tR26\tSIGNED DIV/REM (M-extension) on the fabric: extract signs, run the fabric restoring-division on magnitudes (fabric SLTU + SUB), apply signs (quotient=sa^sb, remainder=sa, round toward zero) == behavioral signed DIV/REM\tnx_rv64im_alu_compute(DIV/REM)\tPRESENT-in-sim\tnx_fpga_sdiv_gate\tsigned DIV+REM over 10 mixed-sign pairs == oracle 0 mismatch incl -100/7=-14 rem -2; fabric division now signed+unsigned; liar-killed. HONEST: MULH/MULHU (high-multiply) the only remaining M-ext op; INT_MIN/-1 overflow not exercised" as *u8 as i64
  keys[27]="fc:FC27" as *u8 as i64; vals[27]="FC27\tR27\tthe SYNTH BRIDGE: serialize the proven LUT4 fabric to a Yosys-synthesizable VERILOG gate-netlist (each cell = a behavioral LUT4 + a machine //@ tag); the layer nishi_hdl_primitives calls 'future' + rv64im_min leaves undone\tnishi-synth (future) / Yosys+nextpnr toolchain\tPRESENT-in-sim\tnx_fpga_verilog_gate\temit the 4-bit ripple-adder fabric -> Verilog; IN-MEMORY ROUND-TRIP: re-parse the //@ tags -> byte-identical fabric (0 diff) that runs on fab_eval computing a+b (15+15=30); liar-kill: corrupt a fabric LUT -> emitted+reparsed netlist computes 3+5=9; never-brick (text only). NEXT: emit the full CPU fabrics + real Yosys/nextpnr/bitstream = the board step" as *u8 as i64
  keys[28]="fc:FC28" as *u8 as i64; vals[28]="FC28\tR28\tSEQUENTIAL synth bridge: the emitter (nx_fpga_verilog lib) serializes CLOCKED fabrics too -- DFF cells -> `reg ff[k]` latched in `always @(posedge clk)`, LUT cells -> combinational assign -- so the WHOLE CPU (regfile/PC are sequential) can be emitted to Verilog, not just logic\tnishi-synth (future) / Yosys+nextpnr\tPRESENT-in-sim\tnx_fpga_verilog_seq_gate\temit a 3-bit counter fabric -> Verilog with always@posedge; round-trip re-parse byte-identical (kind/init/src/po, 0 diff); the RE-PARSED netlist clocked via seq_tick COUNTS 0 1 2 3 4 5 (a working clocked circuit); liar-kill: corrupt the const-1 LUT -> counter stops counting; never-brick. Emitter now factored into lib nx_fpga_verilog (fab_emit_verilog_seq/fab_parse_seq)" as *u8 as i64
  keys[29]="fc:FC29" as *u8 as i64; vals[29]="FC29\tR29\temit a REAL CPU DATAPATH to Verilog: the full 64-bit RV64I ALU (nx_fpga_alu, 576 LUT4 cells -- AND/OR/XOR + add/sub + result-MUX) serializes via the emitter lib to a 75KB Yosys-synthesizable Verilog gate-netlist == behavioral\tnishi-synth (future) / Yosys+nextpnr\tPRESENT-in-sim\tnx_fpga_alu_verilog_gate\temit 576-cell ALU -> 74902 bytes Verilog; round-trip re-parse byte-identical (kind/init/src/po 0 diff); the RE-PARSED netlist (fab_alu_run) computes ADD(5,7)=12/SUB(20,8)=12/AND/OR/XOR(12,10)=6 == oracle 0 mismatch; liar-kill: corrupt the whole ALU LUT config -> ADD diverges. The synth bridge carries REAL CPU logic now, not toys\tNEXT: emit decode/regfile/PC + a top-level CPU module + real Yosys/nextpnr/bitstream (operator hw)" as *u8 as i64
  keys[30]="fc:FC30" as *u8 as i64; vals[30]="FC30\tR30\ta VISIBLE VIRTUAL BOARD (operator: 'a real visible sim like i have the actual board just virtual'): render a virtual ULX3S (8 user LEDs) driven by the simulated fabric -- an 8-bit COUNTER clocked tick by tick -- into a SOVEREIGN 0-JS HTML/SVG page written to web_assets/nishi_virtual_ulx3s.html, openable in the Nishi browser\tULX3S board (visible) / Nishi first-party UI\tPRESENT-in-sim\tnx_fpga_board_gate\t16 frames (ticks 0..15), 8 LED circles each lighting in binary == the real DFF outputs; T1 LEDs==counter every tick 0 mismatch; T2 sovereign 0-<script> + wrote 14480 bytes; liar-kill: corrupt counter -> LEDs stop counting. The board is VISIBLE now, not invisible numbers. NEXT: a live HTTP server (refresh=clock) for interactivity; more peripherals (7-seg/screen); drive it with the CPU" as *u8 as i64
  keys[31]="fc:FC31" as *u8 as i64; vals[31]="FC31\tR31\ta LIVE SELF-RUNNING virtual board: the virtual ULX3S RUNS by itself -- a chain of single-board frames, each a big board (8 LEDs at that tick) carrying an HTML <meta http-equiv=refresh> to the next (looping), so opening board_0.html auto-advances the board ~1fps with NO JS + NO server (sovereign)\tULX3S board (visible/live) / Nishi first-party UI\tPRESENT-in-sim\tnx_fpga_board_anim_gate\twrote web_assets/board_0..15.html; T1 every frame LEDs==counter (0..15) + refresh chains t->(t+1)%16 loops; T2 sovereign 0-<script> all 16 written; liar-killed. Open web_assets/board_0.html -> the board auto-counts, like holding it virtual. NEXT: interactive controls (step/reset/run via 0-JS forms + a serve loop); more peripherals (7-seg/HDMI screen); drive it with the CPU not just a counter" as *u8 as i64
  keys[32]="fc:provenance" as *u8 as i64; vals[32]="authored=organ 2026-06-22..2026-06-23; 31 cells R4-R31 (FPGA-boot sim ladder, hardware-rung-up from the LUT4 spec); ★ the rv64iM INTEGER SET IS COMPLETE IN SIM (full RV64I base + von Neumann memory + BOOTLOADER + ECALL trap + MUL/DIVU/REMU/signed-DIV/REM) AND the SYNTH BRIDGE is open: R27 fabric->Verilog (combinational) + R28 SEQUENTIAL (DFF -> always@posedge) + R29 emits a REAL DATAPATH (the 576-cell 64-bit ALU -> 75KB Verilog == oracle) -> the whole CPU is now emittable to a Yosys-synthesizable gate-netlist; AND R30/R31 make it VISIBLE + LIVE -- a virtual ULX3S (8 LEDs driven by the simulated fabric): R30 a static filmstrip (web_assets/nishi_virtual_ulx3s.html), R31 a SELF-RUNNING animation (web_assets/board_0..15.html, meta-refresh chain, auto-counts ~1fps, 0-JS, no server) you open in the Nishi browser and WATCH run; COMPLEMENTS the structural rv64im_min CPU (boots a real kernel ELF but leaves gate-netlist/PnR/FPGA undone -- THIS arc IS that layer); remaining: interactive board controls (step/reset/run forms + serve loop) + more peripherals (7-seg/HDMI) + drive the board with the CPU + emit decode/regfile/PC + a top-level CPU module + real Yosys/nextpnr/bitstream/board (operator hardware), MULH-family, full-CSR SYSTEM; RAM-decode single-LUT4 R<=16/AB<=4; OMNIFORGE-XREF: SI cells place-and-route/bitstream-encoder/JTAG-loader/physical-FPGA-boot stay ABSENT on REAL METAL (need a board); PRESENT-in-sim, distinct from physical; never-brick by construction; seg-store NOT tsv" as *u8 as i64
  let nrec: i64 = 33
75
  // write absent-or-changed records (idempotent / additive)
  let w: *i64 = ss_begin()
  var towrite: i64 = 0
  var i: i64 = 0
  while i < nrec {
      if fc_streq_store(keys[i] as *u8, vals[i] as *u8, clen(vals[i] as *u8)) == 0 { ss_add(w, 1, keys[i] as *u8, vals[i] as *u8, clen(vals[i] as *u8)); towrite = towrite + 1 }
      i = i + 1
  }
  var committed: i64 = 0
  if towrite > 0 { if ss_commit(FC_PREFIX, w, fc_seg_next_p(FC_PREFIX)) == 0 { committed = 1 } } else { committed = 1 }
86
  // verify EVERY record reads back byte-exact (the store-integrity gate)
  var verified: i64 = 0
  i = 0
  while i < nrec { if fc_streq_store(keys[i] as *u8, vals[i] as *u8, clen(vals[i] as *u8)) == 1 { verified = verified + 1 } i = i + 1 }
91
  cw("  cells=31 records=" as *u8); cn(nrec); cw(" written_this_pass=" as *u8); cn(towrite); cw(" verified=" as *u8); cn(verified); cw(" store=knowledge/store/fpgacen-\n" as *u8)
93
  // GATE-BACK: fork the REAL R9 milestone gate live (must be GREEN) + a neg-control bogus gate (must be non-zero)
  cw("  gate-backing the headline (forking the real gates)...\n" as *u8)
  let r9: i64 = fc_run_gate("nx_fpga_rtype_gate\x00" as *u8)
  let bogus: i64 = fc_run_gate("nx_fpga_bogus_does_not_exist\x00" as *u8)
  cw("  FC08 gate nx_fpga_rtype_gate live-exit=" as *u8); cn(r9); cw(" (expect 0)   neg-control bogus-gate exit=" as *u8); cn(bogus); cw(" (expect non-zero)\n" as *u8)
99
  var ok: i64 = 1
  if verified != nrec { ok = 0 }
  if committed == 0 { ok = 0 }
  if r9 != 0 { ok = 0 }
  if bogus == 0 { ok = 0 }
  if ok == 1 {
      cw("FPGA-CENSUS verdict=GREEN (31-rung FPGA-sim ladder in the sovereign seg-store, byte-verified, gate-backed live; NO TSV; rv64iM COMPLETE + synth bridge fabric->Verilog + a VISIBLE+LIVE self-running virtual ULX3S board)\n" as *u8)
      sys_exit(0); return 0
  }
  cw("FPGA-CENSUS verdict=RED\n" as *u8); sys_exit(1); return 1
110}
nx_fpga_census.nx source

`nx_fpga_census.nx` source
