nx_fpga_rexec.nx source

1// nx_fpga_rexec.nx -- LIB: RUNG 32b -- the R-type ALU-class EXECUTE datapath as ONE composed fabric. 2// 3// Folds the R9 DECODER fabric (nx_fpga_decode: funct3/funct7b5 -> control) and the R8 ALU datapath 4// (nx_fpga_alu: a,b,sub,msel0,msel1 -> result) into a SINGLE fabric via fab_append (R32a), wiring the 5// decoder's {sub,msel0,msel1} control OUTPUTS directly into the ALU's control PIs. The composed fabric 6// takes (funct3 bits, funct7b5, a[W], b[W]) and outputs the W-bit ALU result for the DECODED op -- the 7// control unit + datapath as ONE synthesizable netlist (vs R29 which emitted the ALU alone, no decode). 8// This is the first REAL-CPU-MODULE monolithic fold (toward the whole-CPU CPU.v); shift+compare+result-MUX 9// for the full 10-op R-type are the next rung (R32b-2). Covers the ALU-class ops: ADD/SUB/XOR/OR/AND. 10// NEVER-BRICK (#26): pure memory, bounded (8 + 9W cells), deterministic, zero hardware-state writes. 11// license_tier: ORIGINAL 12import "nx_fpga_compose.nx" 13import "nx_fpga_decode.nx" 14import "nx_fpga_alu.nx" 15import "nx_fpga_fabric.nx" 16import "nx_syscalls.nx" 17const K_MAGIC_2560: i64 = 2560 18 19// Build the composed decode+ALU fabric into cinit/csrc/ckind/cpo. Returns NCELLS (=8+9W). NPI via outnpi. 20// Composed PIs: 0,1,2 = funct3 bits, 3 = funct7b5, 4..3+W = a bits, 4+W..3+2W = b bits. 21func fab_build_rexec_alu(W: i64, cinit: *i64, csrc: *i64, ckind: *i64, cpo: *i64, outnpi: *i64) -> i64 { 22 let NPI: i64 = 4 + 2*W 23 outnpi[0] = NPI 24 let A0: i64 = 4 25 let B0: i64 = 4 + W 26 // --- decoder fabric (npi=4, ncells=8) appended first --- 27 let Di: *i64=sys_mmap(8*16) as *i64; let Ds: *i64=sys_mmap(8*64) as *i64; let Dp: *i64=sys_mmap(8*16) as *i64; let Dk: *i64=sys_mmap(8*16) as *i64 28 let Dnpi: i64 = fab_build_decode(Di, Ds, Dp) 29 var z: i64=0; while z<8 { Dk[z]=0; z=z+1 } 30 let imD: *i64=sys_mmap(8*8) as *i64 31 imD[0]=0; imD[1]=1; imD[2]=2; imD[3]=3 // decode PIs = composed f3_0,f3_1,f3_2,f7b5 32 let baseD: i64 = fab_append(NPI, cinit, csrc, ckind, 0, Dnpi, 8, Di, Ds, Dk, imD) 33 // decoder control outputs (ctrl[0]=sub, [1]=msel0, [2]=msel1) as composed nets 34 let sub_net: i64 = fab_sub_out(NPI, baseD, Dnpi, Dp[0], imD) 35 let m0_net: i64 = fab_sub_out(NPI, baseD, Dnpi, Dp[1], imD) 36 let m1_net: i64 = fab_sub_out(NPI, baseD, Dnpi, Dp[2], imD) 37 // --- ALU fabric (npi=2W+3, ncells=9W) appended second, control PIs wired to the decoder outputs --- 38 let Ai: *i64=sys_mmap(8*640) as *i64; let As: *i64=sys_mmap(8*K_MAGIC_2560) as *i64; let Ap: *i64=sys_mmap(8*72) as *i64; let Ak: *i64=sys_mmap(8*640) as *i64 39 let Anpi: i64 = fab_build_alu(W, Ai, As, Ap) 40 z=0; while z<9*W { Ak[z]=0; z=z+1 } 41 let imA: *i64=sys_mmap(8*(2*W+8)) as *i64 42 var i: i64=0; while i<W { imA[i]=A0+i; imA[W+i]=B0+i; i=i+1 } // ALU a/b PIs <- composed a/b 43 imA[2*W]=sub_net; imA[2*W+1]=m0_net; imA[2*W+2]=m1_net // ALU control PIs <- decoder outputs 44 let baseA: i64 = fab_append(NPI, cinit, csrc, ckind, 8, Anpi, 9*W, Ai, As, Ak, imA) 45 // composed outputs = ALU result bits 46 i=0; while i<W { cpo[i]=fab_sub_out(NPI, baseA, Anpi, Ap[i], imA); i=i+1 } 47 return 8 + 9*W 48} 49 50// evaluate the composed decode+ALU fabric for (funct3,funct7b5,a,b); returns the W-bit result. 51func fab_rexec_run(W: i64, NCELLS: i64, NPI: i64, cinit: *i64, csrc: *i64, cpo: *i64, pi: *i64, co: *i64, f3: i64, f7b5: i64, a: i64, b: i64) -> i64 { 52 pi[0]=f3&1; pi[1]=(f3>>1)&1; pi[2]=(f3>>2)&1; pi[3]=f7b5&1 53 var i: i64=0 54 while i<W { pi[4+i]=(a>>i)&1; pi[4+W+i]=(b>>i)&1; i=i+1 } 55 fab_eval(NCELLS, NPI, cinit, csrc, pi, co) 56 var s: i64=0; i=0 57 while i<W { let bit: i64=fab_resolve(cpo[i], NPI, pi, co); s=s|(bit<<i); i=i+1 } 58 return s 59}