nx_langintel_router.nx source

1// nx_langintel_router.nx -- LangIntel LI6: the ROUTER (LADDER stage 3, actionable). Merges the per-axis 2// count histograms from two sources (rust + llvm) into ONE RANKED capability-requirement registry for 3// NishiLang: one row per axis (excluding the soundness-other catch-all), sorted by total oracle-bug count. 4// Emits <out>: rank TAB axis TAB total TAB GAP TAB note. Each row = a capability the team must build against 5// the measured 0/184 prim void. SUBCLASS of nx_ingest_base. No hw writes (Rule 26). expect_exit: 0 6// argv: <out-plane> <hist-plane-a> <hist-plane-b> 7import "nx_ingest_base.nx" 8import "nx_store_seed_lib.nx" 9import "nx_syscalls.nx" 10 11const LR_CAP: i64 = 1048576 12const LR_OCAP: i64 = 65536 13const LR_MAXVALS: i64 = 512 14const LR_VALSTORE: i64 = 65536 15const LR_TAB: i64 = 9 16const LR_NL: i64 = 10 17const LR_STDERR: i64 = 2 18const LR_MAXCOL: i64 = 8 19const LR_PAIR: i64 = 2 20const LR_SPB: i64 = 128 21const LR_CANDCAP: i64 = 512 22const LR_ARGC_MIN: i64 = 4 23const LR_D0: i64 = 48 24const LR_D9: i64 = 57 25 26static g_valstore: *u8 27static g_vso: i64 28static g_valoff: *i64 29static g_valcnt: *i64 30static g_nvals: i64 31 32func lr_streq(a: *u8, b: *u8) -> i64 { 33 var i: i64 = 0 34 while a[i] != (0 as u8) { if a[i] != b[i] { return 0 } i = i + 1 } 35 if b[i] != (0 as u8) { return 0 } 36 return 1 37} 38func lr_cols(q: *u8, ls: i64, le: i64, sp: *i64) -> i64 { 39 var c: i64 = 0 40 var p: i64 = ls 41 while c < LR_MAXCOL { 42 var e: i64 = p 43 var s: i64 = 1 44 while s == 1 { if e >= le { s = 0 } else { if q[e] == (LR_TAB as u8) { s = 0 } else { e = e + 1 } } } 45 sp[c*LR_PAIR] = p 46 sp[c*LR_PAIR+1] = e 47 c = c + 1 48 if e >= le { return c } 49 p = e + 1 50 } 51 return c 52} 53func lr_atoi_slice(q: *u8, a: i64, b: i64) -> i64 { 54 var v: i64 = 0 55 var i: i64 = a 56 while i < b { let c: i64 = q[i] as i64; if c >= LR_D0 { if c <= LR_D9 { v = v * 10 + (c - LR_D0) } } i = i + 1 } 57 return v 58} 59// process a hist plane buffer: rows are 'count TAB axis'. Add count to that axis in the global table. 60func lr_merge(buf: *u8, n: i64) -> i64 { 61 let sp: *i64 = sys_mmap(LR_SPB) as *i64 62 let cand: *u8 = sys_mmap(LR_CANDCAP) 63 var i: i64 = 0 64 while i < n { 65 var le: i64 = i 66 var s: i64 = 1 67 while s == 1 { if le >= n { s = 0 } else { if buf[le] == (LR_NL as u8) { s = 0 } else { le = le + 1 } } } 68 if le > i { 69 let nc: i64 = lr_cols(buf, i, le, sp) 70 if nc >= 2 { 71 let cnt: i64 = lr_atoi_slice(buf, sp[0], sp[1]) 72 var k: i64 = 0 73 var j: i64 = sp[2] 74 while j < sp[3] { if k < LR_CANDCAP - 1 { cand[k] = buf[j]; k = k + 1 } j = j + 1 } 75 cand[k] = 0 as u8 76 var f: i64 = 0 - 1 77 var t: i64 = 0 78 while t < g_nvals { if lr_streq((g_valstore as i64 + g_valoff[t]) as *u8, cand) == 1 { f = t; t = g_nvals } else { t = t + 1 } } 79 if f >= 0 { g_valcnt[f] = g_valcnt[f] + cnt } 80 else { if g_nvals < LR_MAXVALS { g_valoff[g_nvals] = g_vso; var j2: i64 = 0; while cand[j2] != (0 as u8) { if g_vso < LR_VALSTORE - 2 { g_valstore[g_vso] = cand[j2]; g_vso = g_vso + 1 } j2 = j2 + 1 } g_valstore[g_vso] = 0 as u8; g_vso = g_vso + 1; g_valcnt[g_nvals] = cnt; g_nvals = g_nvals + 1 } } 81 } 82 } 83 i = le + 1 84 } 85 return 0 86} 87 88func main(argc: i64, argv: *i64) -> i64 { 89 if argc < LR_ARGC_MIN { 90 ib_refuse("LANGINTEL-ROUTER" as *u8, "missing args <out-plane> <hist-a> <hist-b>" as *u8, "seed a plan row: 1 TAB nx_langintel_router TAB <out> TAB <hist-a> TAB <hist-b>" as *u8) 91 sys_exit(2) 92 return 2 93 } 94 let outp: *u8 = argv[1] as *u8 95 let ha: *u8 = argv[2] as *u8 96 let hb: *u8 = argv[3] as *u8 97 g_valstore = sys_mmap(LR_VALSTORE) 98 g_vso = 0 99 g_valoff = sys_mmap(LR_MAXVALS * 8) as *i64 100 g_valcnt = sys_mmap(LR_MAXVALS * 8) as *i64 101 g_nvals = 0 102 let bufa: *u8 = sys_mmap(LR_CAP) 103 let na: i64 = sts_load(ha, bufa, LR_CAP) 104 if na <= 0 { ib_refuse("LANGINTEL-ROUTER" as *u8, "hist-a plane EMPTY" as *u8, "run nx_store_hist on the rust axismap first" as *u8); sys_exit(1); return 1 } 105 lr_merge(bufa, na) 106 let bufb: *u8 = sys_mmap(LR_CAP) 107 let nb: i64 = sts_load(hb, bufb, LR_CAP) 108 if nb <= 0 { ib_refuse("LANGINTEL-ROUTER" as *u8, "hist-b plane EMPTY" as *u8, "run nx_store_hist on the llvm axismap first" as *u8); sys_exit(1); return 1 } 109 lr_merge(bufb, nb) 110 var a: i64 = 1 111 while a < g_nvals { 112 var b: i64 = a 113 while b > 0 { 114 if g_valcnt[b-1] < g_valcnt[b] { 115 let tc: i64 = g_valcnt[b-1]; g_valcnt[b-1] = g_valcnt[b]; g_valcnt[b] = tc 116 let to: i64 = g_valoff[b-1]; g_valoff[b-1] = g_valoff[b]; g_valoff[b] = to 117 b = b - 1 118 } else { b = 0 } 119 } 120 a = a + 1 121 } 122 let out: *u8 = sys_mmap(LR_OCAP) 123 var o: i64 = 0 124 var rank: i64 = 1 125 var m: i64 = 0 126 let other: *u8 = "soundness-other" as *u8 127 while m < g_nvals { 128 let ax: *u8 = (g_valstore as i64 + g_valoff[m]) as *u8 129 if lr_streq(ax, other) == 0 { 130 o = ib_bputn(out, o, rank) 131 o = ib_bputc(out, o, LR_TAB) 132 o = ib_bput(out, o, ax) 133 o = ib_bputc(out, o, LR_TAB) 134 o = ib_bputn(out, o, g_valcnt[m]) 135 o = ib_bputc(out, o, LR_TAB) 136 o = ib_bput(out, o, "GAP" as *u8) 137 o = ib_bputc(out, o, LR_TAB) 138 o = ib_bputn(out, o, g_valcnt[m]) 139 o = ib_bput(out, o, " real oracle bugs demand a NishiLang capability on this axis; 0/184 primitives exist -> file a rung" as *u8) 140 o = ib_bputc(out, o, LR_NL) 141 rank = rank + 1 142 } 143 m = m + 1 144 } 145 let rc: i64 = sts_seed(outp, out, o) 146 if rc < 0 { ib_refuse("LANGINTEL-ROUTER" as *u8, "output commit failed" as *u8, "check seg-store for the out plane; retry" as *u8); sys_exit(1); return 1 } 147 ib_werr("LANGINTEL-ROUTER OK verdict=GREEN requirements=" as *u8) 148 ib_wn(LR_STDERR, rank - 1) 149 ib_werr(" -> " as *u8) 150 ib_werr(outp) 151 ib_werr("\n" as *u8) 152 sys_exit(0) 153 return 0 154}