code wiki / _hdl_build / nx_langintel_router.nx
nx_langintel_router.nx
buildroot/runtime/_hdl_build/nx_langintel_router.nx
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nx_langintel_router.nx -- LangIntel LI6: the ROUTER (LADDER stage 3, actionable). Merges the per-axis
count histograms from two sources (rust + llvm) into ONE RANKED capability-requirement registry for
NishiLang: one row per axis (excluding the soundness-other catch-all), sorted by total oracle-bug count.
Emits <out>: rank TAB axis TAB total TAB GAP TAB note. Each row = a capability the team must build against
the measured 0/184 prim void. SUBCLASS of nx_ingest_base. No hw writes (Rule 26). expect_exit: 0
argv: <out-plane> <hist-plane-a> <hist-plane-b>
dependencies 3 imports · 0 importers
imports: nx_ingest_base.nxnx_store_seed_lib.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| 11 | const LR_CAP: i64 = 1048576 |
| 12 | const LR_OCAP: i64 = 65536 |
| 13 | const LR_MAXVALS: i64 = 512 |
| 14 | const LR_VALSTORE: i64 = 65536 |
| 15 | const LR_TAB: i64 = 9 |
| 16 | const LR_NL: i64 = 10 |
| 17 | const LR_STDERR: i64 = 2 |
| 18 | const LR_MAXCOL: i64 = 8 |
| 19 | const LR_PAIR: i64 = 2 |
| 20 | const LR_SPB: i64 = 128 |
| 21 | const LR_CANDCAP: i64 = 512 |
| 22 | const LR_ARGC_MIN: i64 = 4 |
| 23 | const LR_D0: i64 = 48 |
| 24 | const LR_D9: i64 = 57 |
functions
| 32 | func lr_streq(a: *u8, b: *u8) -> i64 |
| 38 | func lr_cols(q: *u8, ls: i64, le: i64, sp: *i64) -> i64 called by 1: lr_merge |
| 53 | func lr_atoi_slice(q: *u8, a: i64, b: i64) -> i64 called by 1: lr_merge |
| 60 | func lr_merge(buf: *u8, n: i64) -> i64 |
| 88 | func main(argc: i64, argv: *i64) -> i64 |