nx_pattern_emit_rtlsynth_demo.nx source

1// nx_pattern_emit_rtlsynth_demo.nx -- DEMO/GATE: the Builder runs the RTL_SYNTH emitter on an op-DAG spec and it 2// AUTHORS a working synthesizer core (shape 23, no Claude logic). Spec = ((in0&in1)+(in0^in1)) over 2 inputs. 3// T1 author succeeds for a valid spec and REFUSES a bad spec (forward src reference). 4// T2 the AUTHORED module is real synthesized dataflow: contains _compute + the baked 'inp[0] & inp[1]' + 't0 + t1'. 5// T3 determinism: re-authoring -> byte-identical module. 6// (Building rs_authored_test via the runner then proves the AUTHORED module COMPILES + PASSES = the autonomy credit.) 7// expect_exit: 0 license_tier: ORIGINAL 8import "nx_pattern_emit_rtlsynth.nx" 9import "nx_syscalls.nx" 10const K_MAGIC_65536: i64 = 65536 11const K_MAGIC_16384: i64 = 16384 12 13func dw(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 14func dn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var m: i64=v; if m<0{sys_write(1,"-" as *u8,1);m=0-m} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } 15func read_all(path: *u8, lenbox: *i64) -> i64 { 16 let fd: i64=sys_openat_rd(path); if fd<0 { lenbox[0]=0; return 0 } 17 let buf: *u8=sys_mmap(K_MAGIC_65536); var off: i64=0; var go: i64=1 18 while go==1 { let r: i64=sys_read(fd, ((buf as i64)+off) as *u8, K_MAGIC_16384); if r<=0 { go=0 } else { off=off+r } } 19 sys_close(fd); lenbox[0]=off; return buf as i64 20} 21func has_sub(hay: *u8, hlen: i64, needle: *u8, nlen: i64) -> i64 { 22 var i: i64=0 23 while i+nlen<=hlen { var j: i64=0; var eq: i64=1; while j<nlen { if hay[i+j]!=needle[j] { eq=0; j=nlen } else { j=j+1 } } if eq==1 { return 1 } i=i+1 } 24 return 0 25} 26 27func main() -> i64 { 28 dw("=== nx_pattern_emit_rtlsynth_demo: the Builder AUTHORS an RTL_SYNTH module from an op-DAG spec (shape 23) ===\n" as *u8) 29 var pass: i64=0; var total: i64=0 30 let mp: *u8="runtime/_hdl_build/rs_authored.nx" as *u8 31 let tp: *u8="runtime/_hdl_build/rs_authored_test.nx" as *u8 32 // spec: ninputs=2, nstmts=3 -> t0=in0&in1, t1=in0^in1, t2=t0+t1 33 let spec: *i64=sys_mmap(128) as *i64 34 spec[0]=2; spec[1]=3 35 spec[2]=0; spec[3]=0; spec[4]=1 36 spec[5]=2; spec[6]=0; spec[7]=1 37 spec[8]=3; spec[9]=2; spec[10]=3 38 let ok: i64=pe_rs_author("rs_authored" as *u8, mp, tp, spec) 39 // bad spec: stmt0 references t0 (forward, src=2 >= ninputs+0=2) -> REFUSE 40 let badspec: *i64=sys_mmap(128) as *i64; badspec[0]=2; badspec[1]=1; badspec[2]=3; badspec[3]=2; badspec[4]=0 41 let bad: i64=pe_rs_author("rs_bad" as *u8, "runtime/_hdl_build/rs_bad.nx" as *u8, "runtime/_hdl_build/rs_bad_test.nx" as *u8, badspec) 42 43 total=total+1; if ok==1 { if bad==0 { pass=pass+1; dw(" [PASS] " as *u8) } else { dw(" [FAIL] " as *u8) } } else { dw(" [FAIL] " as *u8) } 44 dw("T1 AUTHOR+RAIL: valid spec authored=" as *u8); dn(ok); dw(", bad spec (forward src) refused=" as *u8); dn(1-bad); dw("\n" as *u8) 45 46 let lb: *i64=sys_mmap(16) as *i64; let buf: *i64=read_all(mp, lb) 47 let b: *u8=buf as *u8; let blen: i64=lb[0] 48 let h_compute: i64=has_sub(b, blen, "_compute(inp" as *u8, 12) 49 let h_and: i64=has_sub(b, blen, "inp[0] & inp[1]" as *u8, 15) 50 let h_add: i64=has_sub(b, blen, "t0 + t1" as *u8, 7) 51 total=total+1; if h_compute==1 { if h_and==1 { if h_add==1 { pass=pass+1; dw(" [PASS] " as *u8) } else { dw(" [FAIL] " as *u8) } } else { dw(" [FAIL] " as *u8) } } else { dw(" [FAIL] " as *u8) } 52 dw("T2 AUTHORED REAL DATAFLOW: module=" as *u8); dn(blen); dw("B, _compute=" as *u8); dn(h_compute); dw(", 'inp[0] & inp[1]'=" as *u8); dn(h_and); dw(", 't0 + t1'=" as *u8); dn(h_add); dw("\n" as *u8) 53 54 pe_rs_author("rs_authored" as *u8, "runtime/_hdl_build/rs_authored2.nx" as *u8, "runtime/_hdl_build/rs_authored2_test.nx" as *u8, spec) 55 let lb2: *i64=sys_mmap(16) as *i64; let buf2: *i64=read_all("runtime/_hdl_build/rs_authored2.nx" as *u8, lb2) 56 let b2: *u8=buf2 as *u8; var d: i64=0; if lb2[0]!=blen { d=1 } 57 var i: i64=0; while i<blen { if b[i]!=b2[i] { d=d+1 } i=i+1 } 58 total=total+1; if d==0 { pass=pass+1; dw(" [PASS] " as *u8) } else { dw(" [FAIL] " as *u8) } 59 dw("T3 DETERMINISM: re-authoring -> byte-identical module (diffs=" as *u8); dn(d); dw(")\n" as *u8) 60 61 dw("\n AUTONOMY CREDIT: shape 23 RTL_SYNTH is now TEAM-AUTHORABLE -- the Builder lowers an op-DAG to a baked core, no Claude.\n" as *u8) 62 dw("EMIT-RTLSYNTH-DEMO verdict=" as *u8) 63 if pass==total { dw("GREEN passes=" as *u8); dn(pass); dw("/" as *u8); dn(total); dw(" END\n" as *u8); sys_exit(0); return 0 } 64 dw("RED passes=" as *u8); dn(pass); dw("/" as *u8); dn(total); dw(" END\n" as *u8); sys_exit(1); return 1 65}