code wiki / _hdl_build / nx_pattern_emit_rtlsynth_demo.nx

nx_pattern_emit_rtlsynth_demo.nx

buildroot/runtime/_hdl_build/nx_pattern_emit_rtlsynth_demo.nx

4769 B65 linesdepth 3pulls 3 transitivereach 0 importersview sourcekind sketch/demotopic pattern

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nx_pattern_emit_rtlsynth_demo.nx -- DEMO/GATE: the Builder runs the RTL_SYNTH emitter on an op-DAG spec and it AUTHORS a working synthesizer core (shape 23, no Claude logic). Spec = ((in0&in1)+(in0^in1)) over 2 inputs. T1 author succeeds for a valid spec and REFUSES a bad spec (forward src reference). T2 the AUTHORED module is real synthesized dataflow: contains _compute + the baked 'inp[0] & inp[1]' + 't0 + t1'. T3 determinism: re-authoring -> byte-identical module. (Building rs_authored_test via the runner then proves the AUTHORED module COMPILES + PASSES = the autonomy credit.) expect_exit: 0 license_tier: ORIGINAL

dependencies 2 imports · 0 importers

imports: nx_pattern_emit_rtlsynth.nxnx_syscalls.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

structs

none

consts

10	const K_MAGIC_65536: i64 = 65536
11	const K_MAGIC_16384: i64 = 16384

functions

13	func dw(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } called by 1: main calls 1: sys_write
14	func dn(v: i64) -> i64 { let b: u8=sys_mmap(28); var m: i64=v; if m<0{sys_write(1,"-" as u8,1);m=0-m} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{b[i]=t[k-1-i];i=i+1} sys_write(1,b,k); return 0 } called by 1: main calls 2: sys_mmap sys_write
15	func read_all(path: u8, lenbox: i64) -> i64 called by 1: main calls 4: sys_openat_rd sys_mmap sys_read sys_close
21	func has_sub(hay: u8, hlen: i64, needle: u8, nlen: i64) -> i64 called by 1: main
27	func main() -> i64 calls 7: dw sys_mmap pe_rs_author dn read_all has_sub+1