`nx_pm4_asm.nx` source

1// nx_pm4_asm.nx -- sovereign AMD PM4 (GCN/CDNA/RDNA) COMMAND-SUBMISSION encoder = the AMD R1 rung of the
2// "S-class exceed for ANY DEVICE" ladder (the AMD analog of NVIDIA's GPFIFO entry). Second vendor backend.
3//
4// PM4 Type-3 packet header (documented AMD PM4 spec, cross-referenced vs tinygrad ops_amd.py which submits
5// `self.pm4.PACKET3(cmd, len(vals)-1)` packets straight to the MEC -- bypassing the MES scheduler firmware =
6// the MOST-sovereign GPU path per deep-research):
7//   header = (3<<30) | (count<<16) | (opcode<<8)        ; count = number of body DWORDs minus 1
8// IT opcodes below are the stable AMD PM4 values (GFX9-11), used by tinygrad's AM userspace driver.
9// HONEST SCOPE: spec-faithful per the documented AMD PM4 Type-3 format + tinygrad-cross-referenced; toolchain
10// bit-exact verification (llvm-mc -triple=amdgcn, or ROCm) is the UPGRADE (no AMD assembler on this box yet).
11// Pure funcs, no main. license_tier: ORIGINAL
12import "nx_syscalls.nx"
13
14const PM4_IT_DISPATCH_DIRECT: i64 = 0x15
15const PM4_IT_WAIT_REG_MEM:    i64 = 0x3c
16const PM4_IT_RELEASE_MEM:     i64 = 0x49
17const PM4_IT_ACQUIRE_MEM:     i64 = 0x58
18const PM4_IT_SET_SH_REG:      i64 = 0x76
19const PM4_IT_SET_UCONFIG_REG: i64 = 0x79
20
21// PACKET3 Type-3 header (count = body DWORDs - 1).
22func pm4_packet3(opcode: i64, count: i64) -> i64 { return (3 << 30) | ((count & 0x3fff) << 16) | ((opcode & 0xff) << 8) }

nx_pm4_asm.nx source

`nx_pm4_asm.nx` source