nx_q4k_real_gemm.nx source
↩ module page · 131 lines · 6043 B
1// nx_q4k_real_gemm.nx -- the CPU SPEED PATH proven on a REAL Qwen weight: integer fused-dequant-dot vs f32.
2//
3// sd-server -> Nishi migration (CPU perf track, SOTA-grounded: llama.cpp/ggml = quantized-integer GEMM, not
4// emulated f32). Reads the real `Huihui-Qwen3-4B-...-Q4_K_M.gguf`, takes blk.0.attn_q.weight (Q4_K), and
5// computes one output-neuron's projection two ways over row 0:
6// (A) INTEGER path -- `nx_q4k_dot_row_col` (fused dequant+dot, integer Q34 = Q24 weight x Q10 col; the
7// FAST path) -> Q10 -> f32. Q24 super-scales are EXACT (Q10/Q14 underflow/flip-sign on real weights).
8// (B) F32 path -- `nx_q4k_to_f32` (dequant to f32) + our emulated-f32 dot (the CORRECTNESS path).
9// Gates: (1) fused Q34 == manual sum of `nx_gguf_dequant_q4_k` (Q24) x activation (Q10), BIT-EXACT (the fused
10// kernel is correct on real weights); (2) integer(Q24)-path f32 ~ f32-path f32 within ~2%, both ~ +0.21576
11// (the true ggml row-0 dot). Bounded prefix read; only the one row is dequantized.
12// license_tier: ORIGINAL
13import "nx_syscalls.nx"
14import "nx_tier.nx"
15import "nx_le.nx"
16import "nx_strconv.nx"
17import "nx_tensor.nx"
18import "nx_gguf.nx"
19import "nx_gguf_load.nx"
20import "nx_gguf_meta.nx"
21import "nx_placement.nx"
22import "nx_gguf_load_lazy.nx"
23import "nx_q4k_matmul.nx"
24import "nx_dequant_iter.nx"
25import "nx_q4k_to_f32.nx"
26import "nx_f32.nx"
27import "nx_f32_cvt.nx"
28import "nx_f32_div.nx"
29
30func rg_emit(fd: i64, key: *u8, key_len: i64, value: i64) -> i64 {
31 let line: *u8 = sys_mmap(80)
32 var lo: i64 = 0
33 var ki: i64 = 0
34 while ki < key_len { line[lo] = key[ki]; lo = lo + 1; ki = ki + 1 }
35 line[lo] = 0x3D; lo = lo + 1
36 let dec: *u8 = sys_mmap(32)
37 let nd: i64 = nx_strconv_format_i64(value, dec)
38 var k: i64 = 0
39 while k < nd { line[lo] = dec[k]; lo = lo + 1; k = k + 1 }
40 line[lo] = 0x0A; lo = lo + 1
41 return sys_write(fd, line, lo)
42}
43
44func main() -> i64 {
45 let path: *u8 = "/mnt/c/Users/elder/elder-ai-platform/models/unified/text_encoder/Huihui-Qwen3-4B-Instruct-2507-abliterated-Q4_K_M.gguf" as *u8
46 let fd: i64 = sys_openat_rd(path)
47 if fd < 0 { return 30 }
48 let CAP: i64 = 1153433600 // 1.1 GB prefix (blk.0.attn_q is at ~1.04 GB in this model)
49 let buf: *u8 = sys_mmap(CAP)
50 var total: i64 = 0
51 var go: i64 = 1
52 while go == 1 {
53 let r: i64 = sys_read(fd, ((buf as i64) + total) as *u8, CAP - total)
54 if r <= 0 { go = 0 } else { total = total + r; if total >= CAP { go = 0 } }
55 }
56 sys_close(fd)
57 if total < 100000000 { return 31 }
58
59 let hdr: *NxGgufHeader = sys_mmap(NX_GGUF_HDR_BYTES) as *NxGgufHeader
60 if nx_gguf_parse(buf, total, hdr) != NX_GGUF_OK { return 40 }
61 let qi: nx_int = nx_gguf_find_tensor(hdr, "blk.0.attn_q.weight" as *u8, 19)
62 if qi < 0 { return 60 }
63 let ti: *NxGgufTensorInfo = nx_gguf_tensor_at(hdr, qi)
64 let HID: i64 = ti.dim_0
65 let w_off: i64 = hdr.data_off + ti.offset
66
67 // early diagnostics so any failure below is decodable in one run
68 let ofd: i64 = sys_openat_wr("/tmp/zimg_q4k_gemm.txt" as *u8, 0x1a4)
69 if ofd >= 0 {
70 rg_emit(ofd, "ggml_type" as *u8, 9, ti.ggml_type)
71 rg_emit(ofd, "HID" as *u8, 3, HID)
72 rg_emit(ofd, "out_dim" as *u8, 7, ti.dim_1)
73 rg_emit(ofd, "w_off" as *u8, 5, w_off)
74 rg_emit(ofd, "total" as *u8, 5, total)
75 }
76 if ti.ggml_type != 12 { sys_close(ofd); return 61 } // expect Q4_K (12)
77 if HID - (HID / 256) * 256 != 0 { sys_close(ofd); return 62 }
78 let n_blocks: i64 = HID / 256
79 if w_off + n_blocks * 144 > total { sys_close(ofd); return 63 }
80
81 // Q10 activation vector (HID entries): repeating {1.0,1.25,1.5,1.75,2.0}
82 let col: *i64 = sys_mmap(HID * 8) as *i64
83 var i: i64 = 0
84 while i < HID { col[i] = 1024 + (i - (i / 5) * 5) * 256; i = i + 1 }
85
86 // (A) INTEGER fused-dequant-dot (the fast path). Q34 = Q24 weight x Q10 col.
87 let it: *NxQ4KBlockIter = nx_q4k_iter_alloc()
88 let dot_q34: i64 = nx_q4k_dot_row_col(buf, w_off, n_blocks, col, it)
89 let dot_q10: i64 = nx_q4km_q20_to_q10(dot_q34) // >>24 round-half -> Q10
90 let int_f32: i64 = nx_q10_to_f32(dot_q10)
91
92 // GATE 1 (bit-exact): fused Q34 == manual sum of materialized-Q24 weights x Q10 activation.
93 let wq24: *i64 = sys_mmap(HID * 8) as *i64
94 nx_gguf_dequant_q4_k(buf, w_off, HID, wq24) // now emits Q24
95 var ref_q34: i64 = 0
96 i = 0
97 while i < HID { ref_q34 = ref_q34 + wq24[i] * col[i]; i = i + 1 }
98
99 // (B) F32 path: dequant row to f32 + emulated-f32 dot with the SAME activation (Q10 -> exact f32).
100 let wf32: *i64 = sys_mmap(HID * 8) as *i64
101 nx_q4k_to_f32(buf, w_off, HID, wf32)
102 var accf: i64 = 0
103 i = 0
104 while i < HID { accf = nx_f32_add(accf, nx_f32_mul(wf32[i], nx_q10_to_f32(col[i]))); i = i + 1 }
105
106 let absref: i64 = accf & 0x7FFFFFFF
107
108 // GATE 2: integer(Q24) path f32 ~ f32 path within ~2%. Both must be ~ +0.21576 (true ggml row-0 dot).
109 let absdiff: i64 = nx_f32_sub(int_f32, accf) & 0x7FFFFFFF
110 let tolf: i64 = nx_f32_div(nx_i32_to_f32(2), nx_i32_to_f32(100)) // 2%
111 let thresh: i64 = nx_f32_mul(tolf, absref)
112
113 if ofd >= 0 {
114 rg_emit(ofd, "n_blocks" as *u8, 8, n_blocks)
115 rg_emit(ofd, "dot_q34" as *u8, 7, dot_q34)
116 rg_emit(ofd, "ref_q34" as *u8, 7, ref_q34)
117 rg_emit(ofd, "dot_q10" as *u8, 7, dot_q10)
118 rg_emit(ofd, "wq24_0" as *u8, 6, wq24[0])
119 rg_emit(ofd, "wq24_5" as *u8, 6, wq24[5])
120 rg_emit(ofd, "wf32_0_bits" as *u8, 11, wf32[0])
121 rg_emit(ofd, "int_q24_f32_bits" as *u8, 16, int_f32)
122 rg_emit(ofd, "accf_f32_bits" as *u8, 13, accf)
123 rg_emit(ofd, "absdiff_bits" as *u8, 12, absdiff)
124 rg_emit(ofd, "thresh_bits" as *u8, 11, thresh)
125 sys_close(ofd)
126 }
127
128 if ref_q34 != dot_q34 { return 70 } // GATE 1: fused == materialized (both Q34)
129 if absdiff >= thresh { return 80 } // GATE 2: integer(Q24) path ~ f32 path
130 return 0
131}