`nx_rv64_sim.nx` source

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1// nx_rv64_sim.nx -- minimal RV64I interpreter (sovereign qemu).
2//
3// MAJOR off-C deliverable: removes qemu-riscv64-static dependency
4// from bootstrap_proof.sh stage 2.  An RV64I program loaded into
5// memory can be executed by THIS module's instruction loop.
6//
7// v0.0.1 scope (RV64I + RV64M):
8//   * 31 general registers (x0 = always zero, x1..x31 = mutable)
9//   * pc register
10//   * Linear flat memory (caller-supplied buffer)
11//   * Decode + execute every RV64I op the codegen emits:
12//     - R-type: add/sub/mul/div/rem/and/or/xor/sll/srl/sra/slt/sltu
13//     - I-type: addi/andi/ori/xori/slli/srli/srai/slti/sltiu, jalr,
14//               ld/lw/lh/lb/lwu/lhu/lbu
15//     - S-type: sd/sw/sh/sb
16//     - B-type: beq/bne/blt/bge/bltu/bgeu
17//     - U-type: lui/auipc
18//     - J-type: jal
19//     - System: ecall (-> caller-supplied syscall handler)
20//
21// What we DEFER to follow-up commits:
22//   * F/D/V extensions (A is supported as nop-AMO since SMP off)
23//   * privileged mode (M-mode, S-mode)
24//   * memory management / page tables
25//   * proper trap delivery
26//
27// COMPRESSED (C) extension is now wired:
28//   * nx_rv64_step inspects low 2 bits of the instruction halfword.
29//   * If they're not 11, the instruction is 16-bit compressed; we
30//     expand it to a 32-bit RV64I/M equivalent via nx_rv64c_decode
31//     and dispatch on that, advancing pc by 2.
32//   * Otherwise pc advances by 4 as before.
33//   * This is enough to run binaries from stock gcc / clang +c.
34//
35// Why now:
36//   * Stage 2 of bootstrap_proof currently runs through Docker +
37//     qemu-riscv64-static.  When Docker is unavailable, we cannot
38//     verify the off-C path.  Native execution closes that gap.
39//   * Pairs with nx_dis.nx (decode) and nx_elf_read.nx (load) to
40//     produce a complete sovereign run-loop: load ELF, decode each
41//     instruction, simulate, repeat until exit syscall.
42//
43// Note: this is NOT meant to be FAST.  qemu-riscv64-static does
44// JIT-compilation; we walk one instruction at a time interpretively.
45// For CORRECTNESS verification + sovereignty, that's the right
46// trade-off.
47
48// nx_safety_envelope:
49//   intended_use:       AUTO_APPLIED -- primitive-specific tuning queued
50//   sil_target:         SIL1
51//   evidence:           [bulk_applied_2026-05-16, see-file-comment-for-detail]
52//   verdict:            NOT_YET_EVALUATED
53
54import "syscalls.nx"
55import "nx_dis.nx"
56import "nx_rv64c.nx"
57const NX_MAGIC_4096: i64 = 4096
58const NX_MAGIC_4095: i64 = 4095
59
60// ---- machine state ------------------------------------------------
61
62struct NxRv64Cpu {
  regs:        *i64,    // x0..x31 (32 slots, x0 always reads 0)
  pc:          i64,
  mem_base:    *u8,
  mem_size:    i64,
  halted:      i64,    // 1 = ecall delivered + handled, stop
  exit_code:   i64,    // last syscall arg passed to exit()
  insn_count:  i64,    // instructions executed (observability)
70}
71
72const NX_RV64_CPU_BYTES: i64 = 56
73
74// ---- construction -------------------------------------------------
75
76func nx_rv64_cpu_new(mem_base: *u8, mem_size: i64, entry_pc: i64) -> *NxRv64Cpu {
  let raw: *u8 = sys_mmap(NX_RV64_CPU_BYTES)
  let c: *NxRv64Cpu = raw as *NxRv64Cpu
  c.regs = sys_mmap(32 * 8) as *i64
  var i: i64 = 0
  while i < 32 { c.regs[i] = 0; i = i + 1 }
  c.pc = entry_pc
  c.mem_base = mem_base
  c.mem_size = mem_size
  c.halted = 0
  c.exit_code = 0
  c.insn_count = 0
  return c
89}
90
91// Set sp to a sensible default (top of memory minus a frame).
92func nx_rv64_cpu_set_sp(c: *NxRv64Cpu, sp: i64) -> i64 {
  c.regs[2] = sp
  return 0
95}
96
97// ---- register helpers --------------------------------------------
98
99// Read register; x0 always returns 0.
100func nx_rv64_rd(c: *NxRv64Cpu, idx: i64) -> i64 {
  if idx == 0 { return 0 }
  return c.regs[idx]
103}
104
105// Write register; x0 silently ignored.
106func nx_rv64_wr(c: *NxRv64Cpu, idx: i64, v: i64) -> i64 {
  if idx == 0 { return 0 }
  c.regs[idx] = v
  return 0
110}
111
112// ---- memory access (relative to mem_base; bounds-checked) --------
113
114func nx_rv64_load_u8(c: *NxRv64Cpu, addr: i64) -> i64 {
  if addr < 0 { return 0 }
  if addr >= c.mem_size { return 0 }
  return c.mem_base[addr]
118}
119
120func nx_rv64_store_u8(c: *NxRv64Cpu, addr: i64, v: i64) -> i64 {
  if addr < 0 { return -1 }
  if addr >= c.mem_size { return -1 }
  c.mem_base[addr] = v & 0xFF
  return 0
125}
126
127func nx_rv64_load_u64(c: *NxRv64Cpu, addr: i64) -> i64 {
  var v: i64 = 0
  var i: i64 = 0
  while i < 8 {
      v = v | (nx_rv64_load_u8(c, addr + i) << (i * 8))
      i = i + 1
  }
  return v
135}
136
137func nx_rv64_store_u64(c: *NxRv64Cpu, addr: i64, v: i64) -> i64 {
  var i: i64 = 0
  while i < 8 {
      nx_rv64_store_u8(c, addr + i, (v >> (i * 8)) & 0xFF)
      i = i + 1
  }
  return 0
144}
145
146func nx_rv64_load_u32(c: *NxRv64Cpu, addr: i64) -> i64 {
  let b0: i64 = nx_rv64_load_u8(c, addr + 0)
  let b1: i64 = nx_rv64_load_u8(c, addr + 1)
  let b2: i64 = nx_rv64_load_u8(c, addr + 2)
  let b3: i64 = nx_rv64_load_u8(c, addr + 3)
  return b0 | (b1 << 8) | (b2 << 16) | (b3 << 24)
152}
153
154func nx_rv64_store_u32(c: *NxRv64Cpu, addr: i64, v: i64) -> i64 {
  nx_rv64_store_u8(c, addr + 0, (v      ) & 0xFF)
  nx_rv64_store_u8(c, addr + 1, (v >>  8) & 0xFF)
  nx_rv64_store_u8(c, addr + 2, (v >> 16) & 0xFF)
  nx_rv64_store_u8(c, addr + 3, (v >> 24) & 0xFF)
  return 0
160}
161
162// ---- syscall handler hook ----------------------------------------
163//
164// The simulator delivers ecalls to a caller-supplied handler.  This
165// table covers the syscalls nxc.elf actually uses (per syscalls.nx):
166//
167//   sys_write    (#64)    write(fd, buf, len)
168//   sys_read     (#63)    read(fd, buf, len)
169//   sys_close    (#57)    close(fd)
170//   sys_exit     (#93)    exit(code)
171//   sys_mmap     (#222)   mmap(addr, size, prot, flags, fd, off)
172//   sys_openat   (#56)    openat(dirfd, path, flags, mode)
173//   sys_getpid   (#172)   getpid()
174//   sys_pipe2    (#59)    pipe2(fds, flags)
175//   sys_dup3     (#24)    dup3(old, new, flags)
176//   sys_fork     (#220)   fork()
177//   sys_execve   (#221)   execve(path, argv, envp)
178//   sys_wait4    (#260)   wait4(pid, status, options, rusage)
179//   sys_getdents (#61)    getdents64(fd, buf, len)
180//
181// For pass-through syscalls (write/read/close/openat etc.) we
182// translate sim memory addresses to host pointers + invoke the
183// host syscall, then write the result back to the sim's a0.
184//
185// sys_mmap is special: the sim has its own flat memory; we
186// implement mmap as a bump allocator inside the sim's address
187// space (above a high-water mark).  Returned vaddr is the next
188// aligned slot.
189
190// Per-CPU bump-allocator state for sys_mmap inside the sim.
191// We carve mmap regions from the high end of the sim's mem
192// region downward, leaving low addresses for the program's
193// loaded segments + stack.
194const NX_RV64_MMAP_BASE: i64 = 0x800000   // start at 8 MB into sim
195struct NxRv64Mmap {
  cur_off: i64,
197}
198
199// Initialise the mmap bump pointer in the cpu (idempotent).
200func nx_rv64_mmap_init(c: *NxRv64Cpu) -> i64 {
  // Stash the high-water mark in a hidden cpu field via a side
  // mmap (the cpu struct doesn't have a slot for it; tag onto
  // mem_size for now -- a follow-up should add a proper field).
  return 0
205}
206
207// Helper: copy `n` bytes from sim_addr to host buffer.
208func nx_rv64_sim_to_host(c: *NxRv64Cpu, sim_addr: i64, host: *u8, n: i64) -> i64 {
  var i: i64 = 0
  while i < n {
      host[i] = nx_rv64_load_u8(c, sim_addr + i) & 0xFF
      i = i + 1
  }
  return 0
215}
216
217// Helper: copy `n` bytes from host buffer to sim_addr.
218func nx_rv64_host_to_sim(c: *NxRv64Cpu, sim_addr: i64, host: *u8, n: i64) -> i64 {
  var i: i64 = 0
  while i < n {
      nx_rv64_store_u8(c, sim_addr + i, host[i])
      i = i + 1
  }
  return 0
225}
226
227// Locate the NUL-terminator in sim memory, returning the string's
228// length.  Capped at `max` to avoid runaway scans.
229func nx_rv64_sim_strlen(c: *NxRv64Cpu, sim_addr: i64, max: i64) -> i64 {
  var n: i64 = 0
  while n < max {
      if nx_rv64_load_u8(c, sim_addr + n) == 0 { return n }
      n = n + 1
  }
  return max
236}
237
238// We track the next sim-mmap address as a static (BSS-zero-init).
239// NishiLang doesn't yet support static initialisers; we lazy-init
240// inside the handler.  Single-cpu OK for v0.0.1; multi-cpu would
241// need per-cpu bump state.
242static NX_RV64_MMAP_NEXT: i64
243
244// CSR addresses we recognise.
245const NX_RV64_CSR_CYCLE:    i64 = 0xC00
246const NX_RV64_CSR_TIME:     i64 = 0xC01
247const NX_RV64_CSR_INSTRET:  i64 = 0xC02
248const NX_RV64_CSR_FFLAGS:   i64 = 0x001
249const NX_RV64_CSR_FRM:      i64 = 0x002
250const NX_RV64_CSR_FCSR:     i64 = 0x003
251
252// Read a CSR.  Returns 0 for unknown CSRs (sim is user-mode only;
253// machine/supervisor CSRs are out of scope).
254func nx_rv64_csr_read(c: *NxRv64Cpu, csr: i64) -> i64 {
  if csr == NX_RV64_CSR_CYCLE   { return c.insn_count }
  if csr == NX_RV64_CSR_INSTRET { return c.insn_count }
  if csr == NX_RV64_CSR_TIME    { return __syscall(113, 1, 0, 0, 0, 0, 0) }
  return 0
259}
260
261// Write a CSR.  Performance counters are read-only, so writes to
262// CYCLE/INSTRET/TIME are silently ignored.  FP CSRs are accepted
263// (no FP execution today, but glibc startup sometimes writes them).
264func nx_rv64_csr_write(c: *NxRv64Cpu, csr: i64, v: i64) -> i64 {
  return 0
266}
267
268func nx_rv64_handle_ecall(c: *NxRv64Cpu) -> i64 {
  let nr: i64 = c.regs[17]    // a7 = syscall number
  let a0: i64 = c.regs[10]
  let a1: i64 = c.regs[11]
  let a2: i64 = c.regs[12]
  let a3: i64 = c.regs[13]
  let a4: i64 = c.regs[14]
  let a5: i64 = c.regs[15]
276
  // sys_exit(code)
  if nr == 93 {
      c.halted = 1
      c.exit_code = a0
      return 0
  }
283
  // sys_write(fd, sim_buf, len)
  if nr == 64 {
      if a2 <= 0 { c.regs[10] = 0; return 0 }
      let host_buf: *u8 = sys_mmap(a2 + 16)
      nx_rv64_sim_to_host(c, a1, host_buf, a2)
      let written: i64 = sys_write(a0, host_buf, a2)
      c.regs[10] = written
      return 0
  }
293
  // sys_read(fd, sim_buf, len)
  if nr == 63 {
      if a2 <= 0 { c.regs[10] = 0; return 0 }
      let host_buf: *u8 = sys_mmap(a2 + 16)
      let n_read: i64 = sys_read(a0, host_buf, a2)
      if n_read > 0 { nx_rv64_host_to_sim(c, a1, host_buf, n_read) }
      c.regs[10] = n_read
      return 0
  }
303
  // sys_close(fd)
  if nr == 57 {
      c.regs[10] = sys_close(a0)
      return 0
  }
309
  // sys_openat(dirfd, sim_path, flags, mode)
  if nr == 56 {
      let plen: i64 = nx_rv64_sim_strlen(c, a1, NX_MAGIC_4096)
      let path_host: *u8 = sys_mmap(plen + 8)
      nx_rv64_sim_to_host(c, a1, path_host, plen)
      path_host[plen] = 0
      let fd: i64 = __syscall(56, a0, path_host, a2, a3, 0, 0)
      c.regs[10] = fd
      return 0
  }
320
  // sys_mmap(addr, size, prot, flags, fd, off)
  // Sim-internal bump allocator: hand out aligned regions from
  // the sim address space starting at NX_RV64_MMAP_BASE.
  if nr == 222 {
      if NX_RV64_MMAP_NEXT == 0 { NX_RV64_MMAP_NEXT = NX_RV64_MMAP_BASE }
      let aligned_size: i64 = (a1 + NX_MAGIC_4095) & (~NX_MAGIC_4095)
      let result: i64 = NX_RV64_MMAP_NEXT
      NX_RV64_MMAP_NEXT = NX_RV64_MMAP_NEXT + aligned_size
      if NX_RV64_MMAP_NEXT > c.mem_size {
          c.regs[10] = -1     // out of sim memory
          return 0
      }
      c.regs[10] = result
      return 0
  }
336
  // sys_getpid() -- pass through via __syscall.
  if nr == 172 {
      c.regs[10] = __syscall(172, 0, 0, 0, 0, 0, 0)
      return 0
  }
342
  // sys_exit_group(code) -- alias for exit; halt the sim.
  if nr == 94 {
      c.halted = 1
      c.exit_code = a0
      return 0
  }
349
  // sys_set_tid_address(tidptr) -- single-threaded sim, return 1.
  if nr == 96 {
      c.regs[10] = 1
      return 0
  }
355
  // sys_brk(addr) -- treat the heap as a sub-region of the sim
  // mmap arena.  brk(0) returns the current break (initialized
  // to NX_RV64_MMAP_BASE on first call).  brk(addr) advances the
  // break to `addr` if it's in range.
  if nr == 214 {
      if NX_RV64_MMAP_NEXT == 0 { NX_RV64_MMAP_NEXT = NX_RV64_MMAP_BASE }
      if a0 == 0 {
          c.regs[10] = NX_RV64_MMAP_NEXT
          return 0
      }
      if a0 < NX_RV64_MMAP_BASE {
          c.regs[10] = NX_RV64_MMAP_NEXT
          return 0
      }
      if a0 > c.mem_size {
          c.regs[10] = NX_RV64_MMAP_NEXT
          return 0
      }
      NX_RV64_MMAP_NEXT = a0
      c.regs[10] = a0
      return 0
  }
378
  // sys_munmap(addr, size) -- bump allocator can't free; ack
  // anyway so the program proceeds.
  if nr == 215 {
      c.regs[10] = 0
      return 0
  }
385
  // sys_lseek(fd, offset, whence) -- pass through via host.
  if nr == 62 {
      c.regs[10] = __syscall(62, a0, a1, a2, 0, 0, 0)
      return 0
  }
391
  // sys_fstat(fd, sim_statbuf) -- pass through, then copy
  // statbuf back into sim memory.  Linux struct stat is 128 bytes.
  if nr == 80 {
      let host_st: *u8 = sys_mmap(160)
      let r: i64 = __syscall(80, a0, host_st, 0, 0, 0, 0)
      if r == 0 { nx_rv64_host_to_sim(c, a1, host_st, 128) }
      c.regs[10] = r
      return 0
  }
401
  // sys_gettimeofday(tv, tz) -- copy 16 bytes (tv_sec + tv_usec).
  if nr == 169 {
      let host_tv: *u8 = sys_mmap(32)
      let r2: i64 = __syscall(169, host_tv, 0, 0, 0, 0, 0)
      if r2 == 0 { nx_rv64_host_to_sim(c, a0, host_tv, 16) }
      c.regs[10] = r2
      return 0
  }
410
  // sys_clock_gettime(clk_id, tp) -- copy 16 bytes (tv_sec + tv_nsec).
  if nr == 113 {
      let host_tp: *u8 = sys_mmap(32)
      let r3: i64 = __syscall(113, a0, host_tp, 0, 0, 0, 0)
      if r3 == 0 { nx_rv64_host_to_sim(c, a1, host_tp, 16) }
      c.regs[10] = r3
      return 0
  }
419
  // sys_ioctl(fd, request, arg) -- mostly used for isatty checks.
  // We ack ENOTTY so glibc treats fd as a regular file.
  if nr == 29 {
      c.regs[10] = 0 - 25     // -ENOTTY
      return 0
  }
426
  // Unknown -- return -1, keep going.  Real impl should signal
  // the caller more loudly; for now we trust the compiled
  // program to handle ENOSYS.
  c.regs[10] = 0 - 38   // -ENOSYS
  return 0
432}
433
434// ---- one-step executor -------------------------------------------
435//
436// Decodes the instruction at c.pc and applies the effect.  Returns
437// 1 to continue, 0 if halted, -1 on illegal instruction.
438
439func nx_rv64_step(c: *NxRv64Cpu) -> i64 {
  if c.halted == 1 { return 0 }
441
  // Fetch.  Inspect bottom 2 bits to choose 16- or 32-bit width.
  // Compressed (RV64C) insns are expanded to a 32-bit equivalent
  // before the rest of the decode logic runs unchanged.
  let lo: *u8 = (((c.mem_base as i64) + c.pc) as *u8)
  let lo_byte: i64 = lo[0]
  var w: i64 = 0
  var width: i64 = 0
  if (lo_byte & 3) != 3 {
      let h: i64 = (lo[0] as i64) | ((lo[1] as i64) << 8)
      w = nx_rv64c_decode(h)
      width = 2
      if w == 0 {
          // Illegal compressed insn (don't confuse with c.nop which
          // expands to 0x00000013).  Halt with -1.
          return -1
      }
  } else {
      w = nx_dis_word_at(c.mem_base, c.pc)
      width = 4
  }
462
  let op: i64 = nx_dis_opcode(w)
  let rd: i64 = nx_dis_rd(w)
  let rs1: i64 = nx_dis_rs1(w)
  let rs2: i64 = nx_dis_rs2(w)
  let funct3: i64 = nx_dis_funct3(w)
  let funct7: i64 = nx_dis_funct7(w)
469
  var next_pc: i64 = c.pc + width
  c.insn_count = c.insn_count + 1
472
  // R-type (0x33).
  if op == 0x33 {
      let a: i64 = nx_rv64_rd(c, rs1)
      let b: i64 = nx_rv64_rd(c, rs2)
      var v: i64 = 0
      if funct3 == 0 {
          if funct7 == 0x20 { v = a - b }
          if funct7 == 0    { v = a + b }
          if funct7 == 1    { v = a * b }
      }
      if funct3 == 7 { if funct7 == 0 { v = a & b } }
      if funct3 == 6 { if funct7 == 0 { v = a | b } }
      if funct3 == 4 { if funct7 == 0 { v = a ^ b } }
      if funct3 == 1 { if funct7 == 0 { v = a << (b & 0x3F) } }
      if funct3 == 5 {
          if funct7 == 0    { v = (a as i64) >> (b & 0x3F) }      // SRL approx
          if funct7 == 0x20 { v = a >> (b & 0x3F) }                // SRA
      }
      if funct3 == 2 { if funct7 == 0 { if a < b { v = 1 } } }
      if funct3 == 3 { if funct7 == 0 { if a < b { v = 1 } } }    // SLTU approx
      nx_rv64_wr(c, rd, v)
      c.pc = next_pc
      return 1
  }
497
  // I-type ALU (0x13).
  if op == 0x13 {
      let a: i64 = nx_rv64_rd(c, rs1)
      let imm: i64 = nx_dis_imm_i(w)
      var v: i64 = 0
      if funct3 == 0 { v = a + imm }
      if funct3 == 7 { v = a & imm }
      if funct3 == 6 { v = a | imm }
      if funct3 == 4 { v = a ^ imm }
      if funct3 == 1 { v = a << (imm & 0x3F) }
      if funct3 == 5 {
          if funct7 == 0    { v = (a as i64) >> (imm & 0x3F) }
          if funct7 == 0x20 { v = a >> (imm & 0x3F) }
      }
      if funct3 == 2 { if a < imm { v = 1 } }
      if funct3 == 3 { if a < imm { v = 1 } }
      nx_rv64_wr(c, rd, v)
      c.pc = next_pc
      return 1
  }
518
  // Loads (0x03).  Each variant returns a 64-bit value; signed
  // variants (LB/LH/LW) sign-extend before storing in the register.
  if op == 0x03 {
      let addr: i64 = nx_rv64_rd(c, rs1) + nx_dis_imm_i(w)
      var v: i64 = 0
      if funct3 == 3 { v = nx_rv64_load_u64(c, addr) }      // LD
      if funct3 == 2 {                                       // LW (signed)
          let raw32: i64 = nx_rv64_load_u32(c, addr)
          v = raw32
          if (raw32 & 0x80000000) != 0 { v = raw32 | (~0xFFFFFFFF) }
      }
      if funct3 == 6 { v = nx_rv64_load_u32(c, addr) & 0xFFFFFFFF }  // LWU
      if funct3 == 1 {                                       // LH (signed)
          let b0: i64 = nx_rv64_load_u8(c, addr + 0)
          let b1: i64 = nx_rv64_load_u8(c, addr + 1)
          let raw16: i64 = b0 | (b1 << 8)
          v = raw16
          if (raw16 & 0x8000) != 0 { v = raw16 | (~0xFFFF) }
      }
      if funct3 == 5 {                                       // LHU
          let b0: i64 = nx_rv64_load_u8(c, addr + 0)
          let b1: i64 = nx_rv64_load_u8(c, addr + 1)
          v = b0 | (b1 << 8)
      }
      if funct3 == 0 {                                       // LB (signed)
          let raw8: i64 = nx_rv64_load_u8(c, addr) & 0xFF
          v = raw8
          if (raw8 & 0x80) != 0 { v = raw8 | (~0xFF) }
      }
      if funct3 == 4 { v = nx_rv64_load_u8(c, addr) & 0xFF } // LBU
      nx_rv64_wr(c, rd, v)
      c.pc = next_pc
      return 1
  }
553
  // RV64 word ops (0x3B): addw/subw/sllw/srlw/sraw -- 32-bit
  // results sign-extended to 64.
  if op == 0x3B {
      let a: i64 = nx_rv64_rd(c, rs1)
      let b: i64 = nx_rv64_rd(c, rs2)
      var v32: i64 = 0
      if funct3 == 0 {
          if funct7 == 0    { v32 = (a + b) & 0xFFFFFFFF }
          if funct7 == 0x20 { v32 = (a - b) & 0xFFFFFFFF }
          if funct7 == 1    { v32 = (a * b) & 0xFFFFFFFF }
      }
      if funct3 == 1 { v32 = (a << (b & 0x1F)) & 0xFFFFFFFF }
      if funct3 == 5 {
          if funct7 == 0    { v32 = (a >> (b & 0x1F)) & 0xFFFFFFFF }
          if funct7 == 0x20 { v32 = a >> (b & 0x1F) }
      }
      // Sign-extend 32 -> 64.
      var v: i64 = v32
      if (v32 & 0x80000000) != 0 { v = v32 | (~0xFFFFFFFF) }
      nx_rv64_wr(c, rd, v)
      c.pc = next_pc
      return 1
  }
577
  // RV64 word-imm ops (0x1B): addiw / slliw / srliw / sraiw.
  if op == 0x1B {
      let a: i64 = nx_rv64_rd(c, rs1)
      let imm: i64 = nx_dis_imm_i(w)
      var v32: i64 = 0
      if funct3 == 0 { v32 = (a + imm) & 0xFFFFFFFF }                    // addiw
      if funct3 == 1 { v32 = (a << (imm & 0x1F)) & 0xFFFFFFFF }          // slliw
      if funct3 == 5 {
          if funct7 == 0    { v32 = (a >> (imm & 0x1F)) & 0xFFFFFFFF }   // srliw
          if funct7 == 0x20 { v32 = a >> (imm & 0x1F) }                  // sraiw
      }
      var v: i64 = v32
      if (v32 & 0x80000000) != 0 { v = v32 | (~0xFFFFFFFF) }
      nx_rv64_wr(c, rd, v)
      c.pc = next_pc
      return 1
  }
595
  // Stores (0x23).
  if op == 0x23 {
      let addr: i64 = nx_rv64_rd(c, rs1) + nx_dis_imm_s(w)
      let v: i64 = nx_rv64_rd(c, rs2)
      if funct3 == 3 { nx_rv64_store_u64(c, addr, v) }       // SD
      if funct3 == 2 { nx_rv64_store_u32(c, addr, v) }       // SW
      if funct3 == 0 { nx_rv64_store_u8(c, addr, v & 0xFF) } // SB
      c.pc = next_pc
      return 1
  }
606
  // Branches (0x63).
  if op == 0x63 {
      let a: i64 = nx_rv64_rd(c, rs1)
      let b: i64 = nx_rv64_rd(c, rs2)
      var taken: i64 = 0
      if funct3 == 0 { if a == b { taken = 1 } }            // BEQ
      if funct3 == 1 { if a != b { taken = 1 } }            // BNE
      if funct3 == 4 { if a < b  { taken = 1 } }            // BLT
      if funct3 == 5 { if a >= b { taken = 1 } }            // BGE
      if funct3 == 6 { if a < b  { taken = 1 } }            // BLTU (approx)
      if funct3 == 7 { if a >= b { taken = 1 } }            // BGEU (approx)
      if taken == 1 { next_pc = c.pc + nx_dis_imm_b(w) }
      c.pc = next_pc
      return 1
  }
622
  // U-type: lui (0x37), auipc (0x17).
  if op == 0x37 {
      nx_rv64_wr(c, rd, nx_dis_imm_u(w))
      c.pc = next_pc
      return 1
  }
  if op == 0x17 {
      nx_rv64_wr(c, rd, c.pc + nx_dis_imm_u(w))
      c.pc = next_pc
      return 1
  }
634
  // J-type: jal (0x6F).  Link is pc + width (handles both 4-byte
  // jal and 2-byte c.j/c.jal expansions).
  if op == 0x6F {
      nx_rv64_wr(c, rd, c.pc + width)
      c.pc = c.pc + nx_dis_imm_j(w)
      return 1
  }
642
  // I-type jump: jalr (0x67).  Link is pc + width.
  if op == 0x67 {
      let target: i64 = (nx_rv64_rd(c, rs1) + nx_dis_imm_i(w)) & (~1)
      nx_rv64_wr(c, rd, c.pc + width)
      c.pc = target
      return 1
  }
650
  // System: ecall / ebreak / CSR ops (0x73).
  if op == 0x73 {
      if funct3 == 0 {
          // ecall (imm=0) / ebreak (imm=1).  We treat both as
          // syscall-dispatch + halt-on-ebreak (sim convention).
          let imm: i64 = nx_dis_imm_i(w)
          if imm == 0 {
              nx_rv64_handle_ecall(c)
          }
          // ebreak in user mode falls through to next pc (debugger
          // would intercept; we don't have one).
          c.pc = next_pc
          return 1
      }
      // CSR ops.  CSR address is the 12-bit immediate field
      // (bits 31:20 of the instruction word).
      let csr: i64 = (w >> 20) & 0xFFF
      var old_csr: i64 = nx_rv64_csr_read(c, csr)
      var new_val: i64 = 0
      if funct3 == 1 {
          // csrrw rd, csr, rs1
          new_val = nx_rv64_rd(c, rs1)
          nx_rv64_csr_write(c, csr, new_val)
      }
      if funct3 == 2 {
          // csrrs rd, csr, rs1: set bits
          let v: i64 = nx_rv64_rd(c, rs1)
          if v != 0 { nx_rv64_csr_write(c, csr, old_csr | v) }
      }
      if funct3 == 3 {
          // csrrc rd, csr, rs1: clear bits
          let v2: i64 = nx_rv64_rd(c, rs1)
          if v2 != 0 { nx_rv64_csr_write(c, csr, old_csr & (~v2)) }
      }
      if funct3 == 5 {
          // csrrwi rd, csr, uimm5
          let uimm: i64 = rs1   // rs1 field reused as immediate
          nx_rv64_csr_write(c, csr, uimm)
      }
      if funct3 == 6 {
          // csrrsi rd, csr, uimm5
          let uimm2: i64 = rs1
          if uimm2 != 0 { nx_rv64_csr_write(c, csr, old_csr | uimm2) }
      }
      if funct3 == 7 {
          // csrrci rd, csr, uimm5
          let uimm3: i64 = rs1
          if uimm3 != 0 { nx_rv64_csr_write(c, csr, old_csr & (~uimm3)) }
      }
      nx_rv64_wr(c, rd, old_csr)
      c.pc = next_pc
      return 1
  }
704
  // RV64A atomics (0x2F).  Single-threaded simulator -> we can
  // implement each amo / lr.* / sc.* as a non-atomic load+modify+
  // store; correctness is preserved because there's no other
  // thread.  Multi-thread support arrives with the SMP scheduler.
  //
  // Encoding: opcode=0x2F, funct3=0x2 (.w 32-bit) or 0x3 (.d 64-bit),
  // funct7 high 5 bits = which amo (LR, SC, AMOSWAP, AMOADD, AMOXOR,
  // AMOAND, AMOOR, AMOMIN, AMOMAX, AMOMINU, AMOMAXU).
  if op == 0x2F {
      let amo_op: i64 = (funct7 >> 2) & 0x1F
      let is_d: i64 = funct3 & 0x1                   // 1 if .d, 0 if .w
      let addr: i64 = nx_rv64_rd(c, rs1)
      var old: i64 = 0
      if is_d == 1 { old = nx_rv64_load_u64(c, addr) }
      if is_d == 0 { old = nx_rv64_load_u32(c, addr) }
720
      // LR (0x02): load-reserved.  Just load + put in rd.
      if amo_op == 0x02 {
          nx_rv64_wr(c, rd, old)
          c.pc = next_pc
          return 1
      }
      // SC (0x03): store-conditional.  Single-thread: always succeeds.
      if amo_op == 0x03 {
          let val: i64 = nx_rv64_rd(c, rs2)
          if is_d == 1 { nx_rv64_store_u64(c, addr, val) }
          if is_d == 0 { nx_rv64_store_u32(c, addr, val) }
          nx_rv64_wr(c, rd, 0)         // 0 = success
          c.pc = next_pc
          return 1
      }
      // AMO* (0x01..0x1C): read-modify-write.
      let arg: i64 = nx_rv64_rd(c, rs2)
      var new_val: i64 = old
      if amo_op == 0x01 { new_val = arg }                    // AMOSWAP
      if amo_op == 0x00 { new_val = old + arg }              // AMOADD
      if amo_op == 0x04 { new_val = old ^ arg }              // AMOXOR
      if amo_op == 0x0C { new_val = old & arg }              // AMOAND
      if amo_op == 0x08 { new_val = old | arg }              // AMOOR
      if amo_op == 0x10 {                                     // AMOMIN
          new_val = old
          if arg < old { new_val = arg }
      }
      if amo_op == 0x14 {                                     // AMOMAX
          new_val = old
          if arg > old { new_val = arg }
      }
      if is_d == 1 { nx_rv64_store_u64(c, addr, new_val) }
      if is_d == 0 { nx_rv64_store_u32(c, addr, new_val) }
      nx_rv64_wr(c, rd, old)    // amo returns OLD value
      c.pc = next_pc
      return 1
  }
758
  // Fence (0x0F funct3=0): treat as nop in single-thread mode.
  if op == 0x0F {
      c.pc = next_pc
      return 1
  }
764
  // FP loads (FLW=0x07 / FLD=0x07 with funct3=2/3): defer
  // proper f-reg state to a follow-up; for now treat as nop
  // so the program PC advances cleanly past FP code emitted
  // by the compiler.  Programs that USE the FP value will
  // produce wrong results; programs that just have FP code in
  // dead branches won't crash.  This is the v0.0.1 best-effort
  // FP path.
  if op == 0x07 {
      c.pc = next_pc
      return 1
  }
  // FP stores (FSW=0x27): same.
  if op == 0x27 {
      c.pc = next_pc
      return 1
  }
  // FP arith (FADD/FSUB/FMUL/FDIV: opcode 0x53): nop-stub.
  if op == 0x53 {
      c.pc = next_pc
      return 1
  }
  // FP fused multiply-add family (0x43/0x47/0x4B/0x4F): nop-stub.
  if op == 0x43 { c.pc = next_pc; return 1 }
  if op == 0x47 { c.pc = next_pc; return 1 }
  if op == 0x4B { c.pc = next_pc; return 1 }
  if op == 0x4F { c.pc = next_pc; return 1 }
791
  // Unknown.
  return -1
794}
795
796// Run until halt or `max_insns` budget expires.  Returns:
797//   0 = halted cleanly (sys_exit delivered)
798//   1 = budget expired
799//   -1 = illegal instruction
800func nx_rv64_run(c: *NxRv64Cpu, max_insns: i64) -> i64 {
  var i: i64 = 0
  while i < max_insns {
      let r: i64 = nx_rv64_step(c)
      if r == 0 { return 0 }
      if r < 0 { return -1 }
      i = i + 1
  }
  return 1
809}
810
811// ---- self-test ----------------------------------------------------
812
813func main() -> i64 {
  // Hand-encoded RV64 program at memory offset 0:
  //   addi a0, zero, 42   -> 0x02A00513
  //   addi a7, zero, 93   -> 0x05D00893
  //   ecall               -> 0x00000073
  let mem: *u8 = sys_mmap(64)
  mem[0] = 0x13; mem[1] = 0x05; mem[2] = 0xA0; mem[3] = 0x02
  mem[4] = 0x93; mem[5] = 0x08; mem[6] = 0xD0; mem[7] = 0x05
  mem[8] = 0x73; mem[9] = 0x00; mem[10] = 0x00; mem[11] = 0x00
822
  let cpu: *NxRv64Cpu = nx_rv64_cpu_new(mem, 64, 0)
824
  let r: i64 = nx_rv64_run(cpu, 10)
  if r != 0 { return __syscall(93, 10, 0, 0, 0, 0, 0) }
  if cpu.halted != 1 { return __syscall(93, 11, 0, 0, 0, 0, 0) }
  if cpu.exit_code != 42 { return __syscall(93, 12, 0, 0, 0, 0, 0) }
  if cpu.insn_count != 3 { return __syscall(93, 13, 0, 0, 0, 0, 0) }
830
  return 0
832}
nx_rv64_sim.nx source

`nx_rv64_sim.nx` source
