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nx_rv64_sim.nx

buildroot/runtime/nx_rv64_sim.nx

28883 B832 linesdepth 4pulls 5 transitivereach 6 importersview sourcekind tooltopic rv64
docsdependenciesstructsconstsfunctions

about

nx_rv64_sim.nx -- minimal RV64I interpreter (sovereign qemu). MAJOR off-C deliverable: removes qemu-riscv64-static dependency from bootstrap_proof.sh stage 2. An RV64I program loaded into memory can be executed by THIS module's instruction loop. v0.0.1 scope (RV64I + RV64M): * 31 general registers (x0 = always zero, x1..x31 = mutable) * pc register * Linear flat memory (caller-supplied buffer) * Decode + execute every RV64I op the codegen emits: - R-type: add/sub/mul/div/rem/and/or/xor/sll/srl/sra/slt/sltu - I-type: addi/andi/ori/xori/slli/srli/srai/slti/sltiu, jalr, ld/lw/lh/lb/lwu/lhu/lbu - S-type: sd/sw/sh/sb - B-type: beq/bne/blt/bge/bltu/bgeu - U-type: lui/auipc - J-type: jal - System: ecall (-> caller-supplied syscall handler) What we DEFER to follow-up commits: * F/D/V extensions (A is supported as nop-AMO since SMP off) * privileged mode (M-mode, S-mode) * memory management / page tables * proper trap delivery COMPRESSED (C) extension is now wired: * nx_rv64_step inspects low 2 bits of the instruction halfword. * If they're not 11, the instruction is 16-bit compressed; we expand it to a 32-bit RV64I/M equivalent via nx_rv64c_decode and dispatch on that, advancing pc by 2. * Otherwise pc advances by 4 as before. * This is enough to run binaries from stock gcc / clang +c. Why now: * Stage 2 of bootstrap_proof currently runs through Docker + qemu-riscv64-static. When Docker is unavailable, we cannot verify the off-C path. Native execution closes that gap. * Pairs with nx_dis.nx (decode) and nx_elf_read.nx (load) to produce a complete sovereign run-loop: load ELF, decode each

dependencies 3 imports · 6 importers

syscalls.nx nx_dis.nx nx_rv64c.nx nx_rv64_sim.nx nx_dbg.nx nx_nxc_native_wrap.nx nx_smoke_sim.nx nx_sovereign_runner.nx nx_toolchain.nx nxc_native_wrap.nx

imports: syscalls.nxnx_dis.nxnx_rv64c.nx

imported by: nx_dbg.nxnx_nxc_native_wrap.nxnx_smoke_sim.nxnx_sovereign_runner.nxnx_toolchain.nxnxc_native_wrap.nx

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main nx_rv64_cpu_new nx_rv64_run nx_rv64_step nx_rv64c_decode nx_c_decode_q0 nx_c_field nx_c_enc_i nx_c_reg3 nx_c_enc_s nx_c_decode_q1 nx_c_field ↻ nx_c_sext nx_c_enc_i ↻ nx_c_enc_u nx_c_reg3 ↻ nx_c_enc_r nx_c_enc_j nx_c_enc_b nx_c_decode_q2 nx_c_field ↻ nx_c_enc_i ↻ nx_c_enc_r ↻ nx_c_enc_s ↻ nx_dis_word_at nx_dis_opcode nx_dis_rd nx_dis_rs1 nx_dis_rs2 nx_dis_funct3 nx_dis_funct7 nx_rv64_rd nx_rv64_wr nx_dis_imm_i nx_rv64_load_u64 nx_rv64_load_u8 nx_rv64_load_u32 nx_rv64_load_u8 ↻ nx_rv64_load_u8 ↻ nx_dis_imm_s

structs

62struct NxRv64Cpu
195struct NxRv64Mmap

consts

57const NX_MAGIC_4096: i64 = 4096
58const NX_MAGIC_4095: i64 = 4095
72const NX_RV64_CPU_BYTES: i64 = 56
194const NX_RV64_MMAP_BASE: i64 = 0x800000 // start at 8 MB into sim
245const NX_RV64_CSR_CYCLE: i64 = 0xC00
246const NX_RV64_CSR_TIME: i64 = 0xC01
247const NX_RV64_CSR_INSTRET: i64 = 0xC02
248const NX_RV64_CSR_FFLAGS: i64 = 0x001
249const NX_RV64_CSR_FRM: i64 = 0x002
250const NX_RV64_CSR_FCSR: i64 = 0x003

functions

76func nx_rv64_cpu_new(mem_base: *u8, mem_size: i64, entry_pc: i64) -> *NxRv64Cpu
called by 7: mainmainmainmainmainmain+1
92func nx_rv64_cpu_set_sp(c: *NxRv64Cpu, sp: i64) -> i64
called by 5: mainmainmainmainmain
100func nx_rv64_rd(c: *NxRv64Cpu, idx: i64) -> i64
called by 1: nx_rv64_step
106func nx_rv64_wr(c: *NxRv64Cpu, idx: i64, v: i64) -> i64
called by 1: nx_rv64_step
114func nx_rv64_load_u8(c: *NxRv64Cpu, addr: i64) -> i64
called by 5: nx_rv64_load_u64nx_rv64_load_u32nx_rv64_sim_to_hostnx_rv64_sim_strlennx_rv64_step
120func nx_rv64_store_u8(c: *NxRv64Cpu, addr: i64, v: i64) -> i64
called by 4: nx_rv64_store_u64nx_rv64_store_u32nx_rv64_host_to_simnx_rv64_step
127func nx_rv64_load_u64(c: *NxRv64Cpu, addr: i64) -> i64
called by 2: nx_dbg_dump_memnx_rv64_step calls 1: nx_rv64_load_u8
137func nx_rv64_store_u64(c: *NxRv64Cpu, addr: i64, v: i64) -> i64
called by 1: nx_rv64_step calls 1: nx_rv64_store_u8
146func nx_rv64_load_u32(c: *NxRv64Cpu, addr: i64) -> i64
called by 1: nx_rv64_step calls 1: nx_rv64_load_u8
154func nx_rv64_store_u32(c: *NxRv64Cpu, addr: i64, v: i64) -> i64
called by 1: nx_rv64_step calls 1: nx_rv64_store_u8
200func nx_rv64_mmap_init(c: *NxRv64Cpu) -> i64
208func nx_rv64_sim_to_host(c: *NxRv64Cpu, sim_addr: i64, host: *u8, n: i64) -> i64
called by 1: nx_rv64_handle_ecall calls 1: nx_rv64_load_u8
218func nx_rv64_host_to_sim(c: *NxRv64Cpu, sim_addr: i64, host: *u8, n: i64) -> i64
called by 1: nx_rv64_handle_ecall calls 1: nx_rv64_store_u8
229func nx_rv64_sim_strlen(c: *NxRv64Cpu, sim_addr: i64, max: i64) -> i64
called by 1: nx_rv64_handle_ecall calls 1: nx_rv64_load_u8
254func nx_rv64_csr_read(c: *NxRv64Cpu, csr: i64) -> i64
called by 1: nx_rv64_step
264func nx_rv64_csr_write(c: *NxRv64Cpu, csr: i64, v: i64) -> i64
called by 1: nx_rv64_step
268func nx_rv64_handle_ecall(c: *NxRv64Cpu) -> i64
called by 1: nx_rv64_step calls 4: nx_rv64_sim_to_hostsys_readnx_rv64_host_to_simnx_rv64_sim_strlen
439func nx_rv64_step(c: *NxRv64Cpu) -> i64
called by 3: nx_dbg_stepnx_dbg_contnx_rv64_run calls 24: nx_rv64c_decodenx_dis_word_atnx_dis_opcodenx_dis_rdnx_dis_rs1nx_dis_rs2+18
800func nx_rv64_run(c: *NxRv64Cpu, max_insns: i64) -> i64
called by 6: mainmainmainmainmainmain calls 1: nx_rv64_step
813func main() -> i64
calls 2: nx_rv64_cpu_newnx_rv64_run