nx_rv64c.nx

nx_rv64c.nx -- RV64C compressed-instruction decoder. Given a 16-bit RV64C instruction, returns the 32-bit RV64I/M equivalent so nx_rv64_sim can execute it via its existing decode path. This is the minimal change that lets us run binaries produced by stock gcc / clang -- both emit C-extension instructions whenever -march has +c (which is the default on most distros). Without this, every other ld/st/branch in a real binary aborts the simulator. With it, the sim runs unmodified RV64GC code. Encoding reference: RISC-V Unprivileged Spec v20191213-Compressed chapter 16 (https://riscv.org/specifications/), Table 16.4 / 16.5. Layout: bits[1:0] = quadrant (00 / 01 / 10 / 11=non-compressed) bits[15:13] = funct3 within quadrant Approach: - One dispatcher per quadrant (q0_decode / q1_decode / q2_decode) - Each dispatcher pulls funct3 + relevant operand fields, reconstructs a 32-bit RV64I instruction word using the standard R/I/S/B/U/J encoders below. - Helper register-mapping: c.* "rs1'" / "rs2'" / "rd'" fields are 3-bit and map to x8..x15 (s0/s1/a0..a5). Returns the expanded 32-bit instruction on success, or 0 on "illegal compressed insn" (which the caller should treat as a trap / fault). We never return 0 for valid c.nop (which expands to addi x0, x0, 0 = 0x00000013).