code wiki / _hdl_build / nx_sass_control_gate.nx
nx_sass_control_gate.nx source
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1// nx_sass_control_gate.nx -- C0 FRONTIER COMPLETION: the SASS control/scheduler word, RE-decoded + verified.
2// nvdisasm does NOT decode the control codes for sm_120, so this was cracked by differential analysis of the
3// cuobjdump samples (mma_probe2.cu). Layout (24-bit control word = high64[40:63]):
4// [0:3] stall · [4] yield · [5:7] write-barrier(7=none) · [8:10] read-barrier(7=none) · [11] fixed ·
5// [13:18] wait-barrier mask · [19:22] reuse.
6// This gate proves nv_control() reproduces EVERY observed control word from SEMANTIC fields, AND that a COMPLETE
7// instruction (operand + dtype + scheduler) reconstructs BIT-EXACT vs NVIDIA's cuobjdump bytes -- i.e. the
8// sovereign Blackwell assembler can now emit correctly-scheduled instructions, not just operand-correct ones.
9// No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
10import "nx_syscalls.nx"
11import "nx_mma_asm.nx"
12
13func bp(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
14func bx(v: i64) -> i64 { bp("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48 as u8;k=1} while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
15func bd(v: i64) -> i64 { let p: *u8=sys_mmap(1); p[0]=(48+v) as u8; sys_write(1,p,1); return 0 }
16
17func chk(name: *u8, got: i64, ref: i64, st: *i64) -> i64 {
18 bp(" " as *u8); bp(name); bp(" -> " as *u8); bx(got)
19 if got==ref { bp(" == cuobjdump PASS\n" as *u8); st[0]=st[0]+1; return 0 }
20 bp(" != ref " as *u8); bx(ref); bp(" FAIL\n" as *u8); return 0
21}
22
23func main() -> i64 {
24 bp("=== SASS control/scheduler word -- RE-decoded + verified bit-exact (C0 FRONTIER COMPLETION) ===\n" as *u8)
25 let st: *i64 = sys_mmap(8); st[0]=0
26 // control word from semantic fields (stall, yield, wbar, rbar, wait_mask, reuse) -- vs observed cuobjdump values
27 chk("stall6+yield (common) " as *u8, nv_control(6,1,7,7,0,0), 0xff6, st)
28 chk("stall2 no-yield " as *u8, nv_control(2,0,7,7,0,0), 0xfe2, st)
29 chk("wait barrier 0 " as *u8, nv_control(6,1,7,7,1,0), 0x2ff6, st)
30 chk("wait barrier 1 " as *u8, nv_control(6,1,7,7,2,0), 0x4ff6, st)
31 chk("wait barrier 2 " as *u8, nv_control(6,1,7,7,4,0), 0x8ff6, st)
32 chk("wait barrier 3 " as *u8, nv_control(6,1,7,7,8,0), 0x10ff6, st)
33 chk("reuse flag " as *u8, nv_control(6,1,7,7,0,1), 0x80ff6, st)
34 chk("reuse + wait barrier 4" as *u8, nv_control(6,1,7,7,0x10,1), 0xa0ff6, st)
35
36 // THE COMPLETE-INSTRUCTION PROOF: full high64 from SEMANTIC fields == the actual cuobjdump bytes
37 chk("FULL HMMA wait-bar-1 " as *u8, nv_mma_high(NV_RZ, NV_TB_HMMA, nv_control(6,1,7,7,2,0)), 0x004ff600000418ff, st)
38 chk("FULL HMMA reuse " as *u8, nv_mma_high(NV_RZ, NV_TB_HMMA, nv_control(6,1,7,7,0,1)), 0x080ff600000418ff, st)
39
40 // negative control: a different stall MUST change the control word (proves the encoder reads the schedule)
41 var neg_ok: i64 = 0
42 if nv_control(6,1,7,7,0,0) != nv_control(2,1,7,7,0,0) { neg_ok = 1 }
43 bp(" NEG stall6 != stall2 control word: " as *u8); if neg_ok==1 { bp("PASS\n" as *u8) } else { bp("FAIL\n" as *u8) }
44
45 let pass: i64 = st[0]
46 bp("SASS-CONTROL-GATE passed " as *u8); bd(pass/10); bd(pass%10); bp("/10 neg=" as *u8); bd(neg_ok); bp("\n" as *u8)
47 if pass==10 { if neg_ok==1 { bp("verdict=GREEN (SASS scheduler word CRACKED + verified: stall/yield/barriers/reuse decoded, FULL instruction reconstructs bit-exact from semantic fields. The sovereign Blackwell assembler can now emit correctly-SCHEDULED instructions -- C0 instruction-level RE COMPLETE; remaining = cubin container + real silicon [cloud])\n" as *u8); sys_exit(0); return 0 } }
48 bp("verdict=RED\n" as *u8); sys_exit(1); return 1
49}