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nx_sass_control_gate.nx
buildroot/runtime/_hdl_build/nx_sass_control_gate.nx
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nx_sass_control_gate.nx -- C0 FRONTIER COMPLETION: the SASS control/scheduler word, RE-decoded + verified.
nvdisasm does NOT decode the control codes for sm_120, so this was cracked by differential analysis of the
cuobjdump samples (mma_probe2.cu). Layout (24-bit control word = high64[40:63]):
[0:3] stall · [4] yield · [5:7] write-barrier(7=none) · [8:10] read-barrier(7=none) · [11] fixed ·
[13:18] wait-barrier mask · [19:22] reuse.
This gate proves nv_control() reproduces EVERY observed control word from SEMANTIC fields, AND that a COMPLETE
instruction (operand + dtype + scheduler) reconstructs BIT-EXACT vs NVIDIA's cuobjdump bytes -- i.e. the
sovereign Blackwell assembler can now emit correctly-scheduled instructions, not just operand-correct ones.
No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_syscalls.nxnx_mma_asm.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 13 | func bp(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 14 | func bx(v: i64) -> i64 { bp("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48 as u8;k=1} while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 15 | func bd(v: i64) -> i64 { let p: *u8=sys_mmap(1); p[0]=(48+v) as u8; sys_write(1,p,1); return 0 } |
| 17 | func chk(name: *u8, got: i64, ref: i64, st: *i64) -> i64 |
| 23 | func main() -> i64 |