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nx_mma_asm.nx
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about
nx_mma_asm.nx -- sovereign PER-VENDOR tensor-core MMA ASSEMBLER (RE-derived encoders). ONE lib; each vendor
is a set of encoder funcs sharing the same disassemble->decode->encode method. Pure funcs, no main.
NVIDIA Blackwell sm_120 DONE (RE-verified bit-exact vs nvcc -arch=sm_120 -cubin -> cuobjdump -sass,
bench/mma_probe.cu + mma_probe2.cu, 10 samples): HMMA bf16 + IMMA s8 (integer = deterministic = the exceed).
low64 = opcode | Rd<<16 | Ra<<24 | Rb<<32
high64 = Rc | typebits<<8 | control<<40 (Rc=RZ=0xff when no accumulator addend)
AMD MFMA/WMMA + Intel DPAS = future SIBLING encoders added here (same method, swap the instruction).
This is the per-device R4 (tensor-core RE) backend lib for the "S-class exceed for ANY DEVICE" ladder.
license_tier: ORIGINAL
dependencies 1 imports · 4 importers
imports: nx_syscalls.nx
imported by: nx_blackwell_mma_asm_gate.nxnx_mmaemit.nxnx_sass_control_gate.nxnx_sass_sched.nx
structs
| none |
consts
| 14 | const NV_HMMA_16816: i64 = 0x723c // HMMA.16816.F32.BF16 (opcode bits[0:15]) |
| 15 | const NV_IMMA_16816: i64 = 0x7237 // IMMA.16816.S8.S8 (integer, deterministic) |
| 16 | const NV_QMMA_16832: i64 = 0x727a // QMMA.16832.F32.E4M3 (FP8 -- the highest-throughput Blackwell dtype / float ceiling) |
| 17 | const NV_TB_HMMA: i64 = 0x0418 // typebits (high[8:39]) for HMMA.BF16 |
| 18 | const NV_TB_HMMA_F16: i64 = 0x0018 // HMMA.F16 -- SAME opcode 0x723c, dtype in typebits (BF16 sets bit10=0x0400) |
| 19 | const NV_TB_IMMA: i64 = 0x4054 // typebits for IMMA.16816 (k16, .ROW/.COL + type/layout) |
| 20 | const NV_TB_IMMA_K32: i64 = 0x405c // IMMA.16832 (m16n8k32, wider-K int8 -- the deterministic exceed op) vs k16 0x4054 |
| 21 | const NV_TB_QMMA_E4M3: i64 = 0x002c // QMMA.16832 E4M3.E4M3 (FP8) typebits |
| 22 | const NV_RZ: i64 = 0xff // RZ accumulator register (Rc when no addend) |
functions
| 24 | func nv_mma_low(opcode: i64, rd: i64, ra: i64, rb: i64) -> i64 { return opcode | (rd<<16) | (ra<<24) | (rb<<32) } |
| 25 | func nv_mma_high(rc: i64, typebits: i64, control: i64) -> i64 { return rc | (typebits<<8) | (control<<40) } |
| 33 | func nv_control(stall: i64, yield: i64, wbar: i64, rbar: i64, wait_mask: i64, reuse: i64) -> i64 |