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nx_blackwell_mma_asm_gate.nx
buildroot/runtime/_hdl_build/nx_blackwell_mma_asm_gate.nx
about
nx_blackwell_mma_asm_gate.nx -- CUDA-EXCEED roadmap C0: gate for the SOVEREIGN Blackwell tensor-core MMA
assembler. The ENCODER now lives in nx_mma_asm.nx (shared per-vendor lib, debt-free); this gate exercises it.
We RE'd the Blackwell sm_120 encoding from nvcc -arch=sm_120 -cubin -> cuobjdump -sass (bench/mma_probe.cu +
mma_probe2.cu). Field layout (differential-decoded, 10 samples, registers to R44 + Rc accumulator + .reuse):
low64 = opcode | Rd<<16 | Ra<<24 | Rb<<32 ; high64 = Rc | typebits<<8 | control<<40
IMMA = the NO-FLOAT-aligned target (integer tensor cores = DETERMINISTIC = the exceed cuBLAS float can't match).
No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_syscalls.nxnx_mma_asm.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 12 | func bp(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 13 | func bx(v: i64) -> i64 { bp("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48 as u8;k=1} while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 14 | func bd(v: i64) -> i64 { let p: *u8=sys_mmap(1); p[0]=(48+v) as u8; sys_write(1,p,1); return 0 } |
| 16 | func chk(name: *u8, lo: i64, hi: i64, rlo: i64, rhi: i64, st: *i64) -> i64 |
| 22 | func main() -> i64 |