nx_schematic_gate.nx source

1// nx_schematic_gate.nx -- GATE for schematic->netlist (front of the EDA flow). Builds a REAL circuit (a voltage 2// divider: J1 connector + R1 + R2), emits its netlist, and proves it like a real tool: 3// T1 NETLIST -- VIN net has 2 pins, MID has 3, GND has 2 (exact connectivity). 4// T2 ERC CLEAN -- the good circuit has 0 electrical-rule violations. 5// T3 ERC LIAR -- floating a pin raises an ERC violation (real rule bites). 6// T4 NEVER-BRICK-- deterministic ERC re-run. 7// T5 ROUTABLE -- 3 nets are routable (>=2 pins) = 3 routing jobs for place-and-route. 8// T6 HANDOFF -- route one netlist net on the shared router -> routed (schematic -> netlist -> ROUTE, end to end). 9// GREEN iff all pass. Sovereign nx_cc->nxasm, no 3rd-party. expect_exit: 0 license_tier: ORIGINAL 10import "nx_schematic.nx" 11import "nx_pcb_autoroute.nx" 12import "nx_syscalls.nx" 13 14func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 15func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 16func fill(a: *i64, n: i64, v: i64) -> i64 { var i: i64=0; while i<n { a[i]=v; i=i+1 } return 0 } 17 18func main() -> i64 { 19 w("=== nx_schematic_gate: schematic capture -> NETLIST (real circuit: a voltage divider) ===\n" as *u8) 20 var pass: i64 = 0; var total: i64 = 0 21 22 // pins (index): 0=R1.1 1=R1.2 2=R2.1 3=R2.2 4=J1.1 5=J1.2 6=J1.3 ; nets: 0=VIN 1=MID 2=GND 23 let npins: i64 = 7; let nnets: i64 = 3 24 let pin_net: *i64 = sys_mmap(8*8) as *i64 25 pin_net[0]=0; pin_net[1]=1; pin_net[2]=1; pin_net[3]=2; pin_net[4]=0; pin_net[5]=1; pin_net[6]=2 26 let pin_label: *i64 = sys_mmap(8*8) as *i64 27 pin_label[0]="R1.1" as *u8 as i64; pin_label[1]="R1.2" as *u8 as i64; pin_label[2]="R2.1" as *u8 as i64 28 pin_label[3]="R2.2" as *u8 as i64; pin_label[4]="J1.1" as *u8 as i64; pin_label[5]="J1.2" as *u8 as i64; pin_label[6]="J1.3" as *u8 as i64 29 let net_name: *i64 = sys_mmap(8*4) as *i64 30 net_name[0]="VIN" as *u8 as i64; net_name[1]="MID" as *u8 as i64; net_name[2]="GND" as *u8 as i64 31 32 // emit the netlist 33 w(" --- NETLIST ---\n" as *u8) 34 var n: i64 = 0 35 while n < nnets { 36 w(" " as *u8); w(net_name[n] as *u8); w(":" as *u8) 37 var p: i64 = 0 38 while p < npins { if pin_net[p] == n { w(" " as *u8); w(pin_label[p] as *u8) } p = p + 1 } 39 w("\n" as *u8) 40 n = n + 1 41 } 42 43 // T1 netlist correctness 44 let vin: i64 = sch_net_pincount(pin_net, npins, 0) 45 let mid: i64 = sch_net_pincount(pin_net, npins, 1) 46 let gnd: i64 = sch_net_pincount(pin_net, npins, 2) 47 total=total+1 48 if vin==2 { if mid==3 { if gnd==2 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } } else { w(" [FAIL] " as *u8) } } else { w(" [FAIL] " as *u8) } 49 w("T1 netlist: VIN=" as *u8); wn(vin); w(" MID=" as *u8); wn(mid); w(" GND=" as *u8); wn(gnd); w(" pins (exact connectivity)\n" as *u8) 50 51 // T2 ERC clean 52 let erc: i64 = sch_erc(pin_net, npins, nnets) 53 total=total+1; if erc == 0 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } 54 w("T2 ERC clean: violations=" as *u8); wn(erc); w(" (no floating pins, no single-pin nets)\n" as *u8) 55 56 // T3 ERC liar-kill: float J1.2 57 pin_net[5] = 0 - 1 58 let erc2: i64 = sch_erc(pin_net, npins, nnets) 59 total=total+1; if erc2 > 0 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } 60 w("T3 ERC liar-kill: floating a pin -> violations=" as *u8); wn(erc2); w(" (real rule bites)\n" as *u8) 61 pin_net[5] = 1 62 63 // T4 never-brick 64 let e1: i64 = sch_erc(pin_net, npins, nnets) 65 let e2: i64 = sch_erc(pin_net, npins, nnets) 66 total=total+1; if e1 == e2 { if e1 == 0 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } } else { w(" [FAIL] " as *u8) } 67 w("T4 never-brick: deterministic ERC (" as *u8); wn(e1); w("==" as *u8); wn(e2); w(")\n" as *u8) 68 69 // T5 routable nets 70 let rn: i64 = sch_routable_nets(pin_net, npins, nnets) 71 total=total+1; if rn == 3 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } 72 w("T5 routable nets = " as *u8); wn(rn); w(" (routing jobs handed to place-and-route)\n" as *u8) 73 74 // T6 handoff: route the VIN net (2 pins) on the shared router -> routed 75 let W: i64 = 4; let H: i64 = 4 76 let nh: i64 = H*(W-1); let nv: i64 = (H-1)*W 77 let ax: *i64=sys_mmap(8*4) as *i64; let ay: *i64=sys_mmap(8*4) as *i64 78 let bx: *i64=sys_mmap(8*4) as *i64; let by: *i64=sys_mmap(8*4) as *i64 79 let cap_h: *i64=sys_mmap(8*64) as *i64; let cap_v: *i64=sys_mmap(8*64) as *i64 80 let block: *i64=sys_mmap(8*64) as *i64; let ub: *i64=sys_mmap(8*64) as *i64 81 let vis: *i64=sys_mmap(8*64) as *i64; let came: *i64=sys_mmap(8*64) as *i64 82 let q: *i64=sys_mmap(8*64) as *i64; let pathbuf: *i64=sys_mmap(8*64) as *i64 83 let sh: *i64=sys_mmap(8*2) as *i64; let ok: *i64=sys_mmap(8*2) as *i64 84 // place VIN's two pins (R1.1, J1.1) at two board sites and route the connection 85 ax[0]=0; ay[0]=0; bx[0]=3; by[0]=2 86 fill(cap_h, nh, 8); fill(cap_v, nv, 8) 87 pa_route_board(1, ax, ay, bx, by, W, H, cap_h, cap_v, block, ub, vis, came, q, pathbuf, 1, sh, ok) 88 total=total+1; if ok[0] == 1 { pass=pass+1; w(" [PASS] " as *u8) } else { w(" [FAIL] " as *u8) } 89 w("T6 handoff: routed the VIN net on the shared router routed=" as *u8); wn(ok[0]); w(" (schematic -> netlist -> ROUTE, end to end)\n" as *u8) 90 91 w("\n=== nx_schematic_gate " as *u8); wn(pass); w("/" as *u8); wn(total) 92 if pass == total { w(" GREEN (schematic->netlist: real circuit, exact connectivity, ERC, routable handoff; the EDA front-end twin)\n" as *u8); sys_exit(0); return 0 } 93 w(" RED\n" as *u8); sys_exit(1); return 1 94}