code wiki / _hdl_build / nx_schematic_gate.nx
nx_schematic_gate.nx
buildroot/runtime/_hdl_build/nx_schematic_gate.nx
about
nx_schematic_gate.nx -- GATE for schematic->netlist (front of the EDA flow). Builds a REAL circuit (a voltage
divider: J1 connector + R1 + R2), emits its netlist, and proves it like a real tool:
T1 NETLIST -- VIN net has 2 pins, MID has 3, GND has 2 (exact connectivity).
T2 ERC CLEAN -- the good circuit has 0 electrical-rule violations.
T3 ERC LIAR -- floating a pin raises an ERC violation (real rule bites).
T4 NEVER-BRICK-- deterministic ERC re-run.
T5 ROUTABLE -- 3 nets are routable (>=2 pins) = 3 routing jobs for place-and-route.
T6 HANDOFF -- route one netlist net on the shared router -> routed (schematic -> netlist -> ROUTE, end to end).
GREEN iff all pass. Sovereign nx_cc->nxasm, no 3rd-party. expect_exit: 0 license_tier: ORIGINAL
dependencies 3 imports · 0 importers
imports: nx_schematic.nxnx_pcb_autoroute.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 14 | func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 15 | func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 16 | func fill(a: *i64, n: i64, v: i64) -> i64 { var i: i64=0; while i<n { a[i]=v; i=i+1 } return 0 } called by 1: main |
| 18 | func main() -> i64 |