code wiki / _hdl_build / nx_tier_gate.nx

nx_tier_gate.nx source

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1// nx_tier_gate.nx -- CONTRACT GATE for nx_tier (arch-board w22 queue row #2: 2,864 importers, gen-0 2// hardware anchor, blast radius 96%). nx_tier is the substrate's TYPE CONTRACT (nx_int/nx_size semantic 3// aliases + tier config); its sworn invariants today are: 64-bit two's-complement default arithmetic, 4// 8-byte memory stride for i64 indexing, little-endian byte order. A DELIBERATE tier swap (i64->i128) 5// changes these -- this gate goes RED so the swap is a reviewed decision, never an accident. That is 6// the base-change contract (mom-3) made mechanical for the type anchor. 7// nx_tier_gate -- exit 0 GREEN / 1 RED 8// license_tier: ORIGINAL module: nishi-core.examiner.tier_gate No hw writes (rule 26). 9import "nx_syscalls.nx" 10import "nx_tier.nx" 11 12func tg2_p(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 } 13func tg2_row(name: *u8, ok: i64, fails: *i64) -> i64 { 14 if ok == 1 { tg2_p(" [PASS] " as *u8) } else { tg2_p(" [FAIL] " as *u8); fails[0] = fails[0] + 1 } 15 tg2_p(name); tg2_p("\n" as *u8) 16 return 0 17} 18 19func main(argc: i64, argv: *i64) -> i64 { 20 tg2_p("=== nx_tier GATE -- the type-anchor contract (tier swap must be deliberate) ===\n" as *u8) 21 let fails: *i64 = sys_mmap(16) as *i64 22 fails[0] = 0 23 24 // T1 default integer is 64-bit two's complement: (1<<62) is positive; doubling it wraps negative. 25 var ok: i64 = 0 26 let big: i64 = 4611686018427387904 27 if big > 0 { if big + big < 0 { ok = 1 } } 28 tg2_row("T1 64-bit two's-complement wrap at 2^63" as *u8, ok, fails) 29 30 // T2 memory stride: i64 indexing steps 8 bytes (nx_size pointer-width contract). 31 ok = 0 32 let arr: *i64 = sys_mmap(32) as *i64 33 arr[0] = 0 34 arr[1] = 4386 35 let bp: *u8 = arr as *u8 36 if bp[8] == (34 as u8) { if bp[9] == (17 as u8) { ok = 1 } } 37 tg2_row("T2 i64 index stride = 8 bytes" as *u8, ok, fails) 38 39 // T3 little-endian byte order: 0x11223344 stores 0x44 first. 40 ok = 0 41 let w: *i64 = sys_mmap(16) as *i64 42 w[0] = 287454020 43 let wb: *u8 = w as *u8 44 if wb[0] == (68 as u8) { if wb[1] == (51 as u8) { if wb[2] == (34 as u8) { if wb[3] == (17 as u8) { ok = 1 } } } } 45 tg2_row("T3 little-endian store order" as *u8, ok, fails) 46 47 // T4 division/modulo identity on the default tier: a == (a/b)*b + a%b for a mixed-sign probe set. 48 ok = 1 49 let pa: *i64 = sys_mmap(64) as *i64 50 pa[0] = 7; pa[1] = 0 - 7; pa[2] = 4611686018427387904; pa[3] = 12345678901 51 var i: i64 = 0 52 while i < 4 { 53 let a: i64 = pa[i] 54 let b: i64 = 13 55 if (a / b) * b + (a % b) != a { ok = 0 } 56 i = i + 1 57 } 58 tg2_row("T4 div/mod identity across mixed signs" as *u8, ok, fails) 59 60 if fails[0] == 0 { tg2_p("=== GATE verdict=GREEN: the type anchor holds (a tier swap will turn this RED on purpose) ===\n" as *u8); return 0 } 61 tg2_p("=== GATE verdict=RED: type-anchor contract violated ===\n" as *u8) 62 return 1 63}