code wiki / _hdl_build / nx_tier_gate.nx

nx_tier_gate.nx

buildroot/runtime/_hdl_build/nx_tier_gate.nx

2964 B63 linesdepth 2pulls 2 transitivereach 0 importersview sourcekind gate/prooftopic tier
docsdependenciesstructsconstsfunctions

about

nx_tier_gate.nx -- CONTRACT GATE for nx_tier (arch-board w22 queue row #2: 2,864 importers, gen-0 hardware anchor, blast radius 96%). nx_tier is the substrate's TYPE CONTRACT (nx_int/nx_size semantic aliases + tier config); its sworn invariants today are: 64-bit two's-complement default arithmetic, 8-byte memory stride for i64 indexing, little-endian byte order. A DELIBERATE tier swap (i64->i128) changes these -- this gate goes RED so the swap is a reviewed decision, never an accident. That is the base-change contract (mom-3) made mechanical for the type anchor. nx_tier_gate -- exit 0 GREEN / 1 RED license_tier: ORIGINAL module: nishi-core.examiner.tier_gate No hw writes (rule 26).

dependencies 2 imports · 0 importers

nx_syscalls.nx nx_tier.nx nx_tier_gate.nx

imports: nx_syscalls.nxnx_tier.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main tg2_p sys_write sys_mmap nxa_die sys_write ↻ sys_exit nxa_lock_take nxa_lock_addr sys_write ↻ nxa_lock_give nxa_lock_addr ↻ nxa_report_overrun sys_write ↻ nxa_dump_printable sys_write ↻ nxa_dump_sizes sys_write ↻ tg2_row tg2_p ↻

structs

none

consts

none

functions

12func tg2_p(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
called by 2: tg2_rowmain calls 1: sys_write
13func tg2_row(name: *u8, ok: i64, fails: *i64) -> i64
called by 1: main calls 1: tg2_p
19func main(argc: i64, argv: *i64) -> i64
calls 3: tg2_psys_mmaptg2_row