nx_vc_fecwire_gate.nx source

1// nx_vc_fecwire_gate.nx -- end-to-end gate for the TIER-2 substrate in the core: frame -> 10 wire 2// shards (vc_fecs_pack) -> lossy OUT-OF-ORDER delivery -> collector (vc_fecrx_add) -> byte-exact 3// frame. Exercises the REAL wire contract the striped legs will carry: 4// T1 pack: 10 self-describing shards (16B fwire header + S), slot size = 16+S 5// T2 lossy out-of-order reassembly: drop 2 shards, feed the rest shuffled -> completes exactly at 6// the 8th shard with the frame BYTE-EXACT (flen 11731 = non-multiple-of-8, padding exercised) 7// T3 duplicate shard ignored (returns 0, no double-delivery) 8// T4 straggler of a SUPERSEDED block dropped (newer block_id wins -- per-frame FEC semantics) 9// T5 NEG over-bound: 3 drops -> the block NEVER completes (honest bound) 10// T6 NEG malformed: wrong k byte -> -1 11// Evidence -> knowledge/status/vc_fecwire.log. expect_exit: 0 license_tier: ORIGINAL 12import "nx_syscalls.nx" 13import "nx_video_client_wasm.nx" 14 15func gw2(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd,s,n); return 0 } 16func gn2(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(fd,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1} sys_write(fd,bb,k); return 0 } 17func chk3(name: *u8, ok: i64, pass: *i64) -> i64 { 18 gw2(1, " " as *u8) 19 if ok==1 { gw2(1, "PASS " as *u8); pass[0]=pass[0]+1 } else { gw2(1, "FAIL " as *u8) } 20 gw2(1, name); gw2(1, "\n" as *u8) 21 return 0 } 22 23func main() -> i64 { 24 gw2(1, "=== nx_vc_fecwire_gate: frame -> shards -> lossy out-of-order -> byte-exact frame ===\n") 25 let pass: *i64 = sys_mmap(16) as *i64 26 pass[0]=0 27 let tbl: *i64 = sys_mmap(8 * 900) as *i64 28 vc_fec_init(tbl) 29 let flen: i64 = 11731 // JPEG-like, NOT a multiple of 8 (padding path) 30 let frame: *u8 = sys_mmap(flen + 64) 31 var i: i64 = 0 32 while i < flen { frame[i] = ((i * 131 + (i / 89) * 3 + 55) & 255) as u8; i = i + 1 } 33 let S: i64 = vc_fecs_shard_size(flen) // 1467 34 let sd: *u8 = sys_mmap(10 * S + 64) 35 let ss: *u8 = sys_mmap(10 * S + 64) 36 let shards: *u8 = sys_mmap(10 * (16 + S) + 64) 37 let slot: i64 = vc_fecs_pack(tbl, frame, flen, 7001, sd, ss, shards) 38 39 // T1 pack shape 40 var t1: i64 = 0 41 if slot == 16 + S { 42 if (shards[4] as i64) == 0 { if (shards[slot + 4] as i64) == 1 { // shard_idx 0 then 1 43 if (shards[9 * slot + 5] as i64) == 1 { t1 = 1 } // last shard is parity 44 } } 45 } 46 chk3("T1 pack: 10 self-describing shards, slot=16+S " as *u8, t1, pass) 47 48 // T2 lossy out-of-order reassembly (drop shards 3 and 7; feed order 9,0,5,2,8,1,6,4) 49 let st: *i64 = sys_mmap(192 + 10 * S + 64) as *i64 50 vc_fecrx_reset(st) 51 let scrA: *i64 = sys_mmap(8 * 64) as *i64 52 let scrSh: *u8 = sys_mmap(10 * S + 64) 53 let out: *u8 = sys_mmap(10 * S + 64) 54 let order: *i64 = sys_mmap(8 * 8) as *i64 55 order[0]=9; order[1]=0; order[2]=5; order[3]=2; order[4]=8; order[5]=1; order[6]=6; order[7]=4 56 var t2: i64 = 0 57 var completed_at: i64 = 0 - 1 58 i = 0 59 while i < 8 { 60 let rc: i64 = vc_fecrx_add(st, tbl, shards + order[i] * slot, slot, scrA, scrSh, out, 10 * S + 64) 61 if rc == flen { completed_at = i } 62 if rc == (0 - 1) { completed_at = 0 - 2; i = 8 } 63 i = i + 1 64 } 65 if completed_at == 7 { 66 var same: i64 = 1 67 var q: i64 = 0 68 while q < flen { if out[q] != frame[q] { same = 0; q = flen } else { q = q + 1 } } 69 t2 = same 70 } 71 chk3("T2 drop-2 out-of-order: completes at 8th, byte-exact " as *u8, t2, pass) 72 73 // T3 duplicate ignored (block done -> straggler of same block returns 0) 74 var t3: i64 = 0 75 if vc_fecrx_add(st, tbl, shards + 0 * slot, slot, scrA, scrSh, out, 10 * S + 64) == 0 { t3 = 1 } 76 chk3("T3 duplicate/post-complete shard ignored " as *u8, t3, pass) 77 78 // T4 supersede: a NEWER block resets the collector; then an OLD straggler drops 79 let shards2: *u8 = sys_mmap(10 * (16 + S) + 64) 80 vc_fecs_pack(tbl, frame, flen, 7002, sd, ss, shards2) 81 var t4: i64 = 0 82 if vc_fecrx_add(st, tbl, shards2 + 2 * slot, slot, scrA, scrSh, out, 10 * S + 64) == 0 { 83 if st[0] == 7002 { 84 if vc_fecrx_add(st, tbl, shards + 5 * slot, slot, scrA, scrSh, out, 10 * S + 64) == 0 { 85 if st[0] == 7002 { t4 = 1 } 86 } 87 } 88 } 89 chk3("T4 newer block supersedes; stale straggler dropped " as *u8, t4, pass) 90 91 // T5 NEG over-bound: fresh collector, feed only 7 shards (3 dropped) -> never completes 92 vc_fecrx_reset(st) 93 var t5: i64 = 1 94 i = 0 95 while i < 7 { 96 let rc2: i64 = vc_fecrx_add(st, tbl, shards + i * slot, slot, scrA, scrSh, out, 10 * S + 64) 97 if rc2 == flen { t5 = 0 } 98 i = i + 1 99 } 100 chk3("T5 NEG 3 losses: block never completes (honest bound)" as *u8, t5, pass) 101 102 // T6 NEG malformed: corrupt the k byte -> -1 103 let bad: *u8 = sys_mmap(slot + 16) 104 i = 0 105 while i < slot { bad[i] = shards[i]; i = i + 1 } 106 bad[6] = 9 as u8 107 var t6: i64 = 0 108 if vc_fecrx_add(st, tbl, bad, slot, scrA, scrSh, out, 10 * S + 64) == (0 - 1) { t6 = 1 } 109 chk3("T6 NEG malformed header rejected (-1) " as *u8, t6, pass) 110 111 gw2(1, "VC-FECWIRE-GATE pass="); gn2(1, pass[0]); gw2(1, "/6") 112 let lf: i64 = sys_openat_append("knowledge/status/vc_fecwire.log" as *u8, 420) 113 if lf >= 0 { 114 gw2(lf, "VCFECWIRE flen="); gn2(lf, flen); gw2(lf, " S="); gn2(lf, S); gw2(lf, " pass="); gn2(lf, pass[0]); gw2(lf, "/6") 115 if pass[0]==6 { gw2(lf, " verdict=GREEN\n") } else { gw2(lf, " verdict=RED\n") } 116 sys_close(lf) 117 } 118 if pass[0]==6 { gw2(1, " verdict=GREEN -- the striped-leg wire substrate is proven end-to-end in the core\n"); return 0 } 119 gw2(1, " verdict=RED\n") 120 return 1 121}