nx_atom.nx

nx_atom.nx -- atomic primitives + memory ordering. FOUNDATION LAYER. Every lock-free data structure, every SMP-safe counter, every message queue in NishiOS sits on top of these operations: load, store, CAS, FAA, and memory barriers. Why now (DARPA-class concurrency correctness): The current observability stack (nx_log, nx_trace, nx_metrics, nx_arena, nx_ring, nx_id) is single-threaded-only. The moment NishiOS ships its SMP scheduler, every one of those modules either gains an atomic primitive or silently corrupts. Land the primitive FIRST -- mechanical retrofit, not rescue. seL4 / Nemesis lineage: concurrency correctness is the second-highest cost in kernel verification (after memory safety). seL4's proof rests on a uniprocessor model; the multi-core extension (MCS seL4) required re-proving sizable chunks around synchronisation primitives. Getting the atomic memory model RIGHT AT THE SOURCE LANGUAGE LAYER pays that cost once. MEMORY ORDERING TAXONOMY (RV64A, C11 atomic_*, Rust atomic_*): NX_MO_RELAXED No ordering. Counter bumps. Fastest. NX_MO_CONSUME Data-dependent loads (C11 intent; rarely used). NX_MO_ACQUIRE Load-acquire: no load/store after this op can migrate BEFORE it. Standard lock acquire. NX_MO_RELEASE Store-release: no load/store before this op can migrate AFTER it. Standard lock release. NX_MO_ACQ_REL Both -- used on RMW (read-modify-write) ops. NX_MO_SEQ_CST Sequential consistency: single global order across all seq-cst ops on the machine. Slowest. Default for userland until profiling warrants weaker ordering. RV64A MAPPING (RISC-V A extension) -- emit targets when nxc2 grows inline asm: load-acquire lr.d / ld + fence r,rw (aq bit on lr.d)