nx_parallel_simd_reduce.nx

nx_parallel_simd_reduce.nx -- proof of L7 x L8 composition. nx_parallel_reduce_i64 splits the array across worker threads; each worker reduces its chunk using __simd_vreduce_sum_i64_x4 (4 lanes at a time). The orchestrator combines per-chunk results into the final sum. Bit-exact vs scalar baseline. In Flynn-taxonomy terms this is exactly the HPC stack pattern the user named: MIMD across cores + SIMD inside each core = N_cores x 4-lane speedup over scalar single-core on real silicon. Under qemu the MIMD axis is fake (single CPU) and the SIMD axis is interpretive overhead, so the wall-time will LOSE vs scalar -- but the CORRECTNESS gate is hard.