nx_calibrate.nx

nx_calibrate.nx -- lmbench-class empirical cost-model builder. SA-2 milestone of NISHI_SELF_ASSEMBLY_ROADMAP.md. Consumes the device capability fingerprint from nx_probe and produces an empirical cost model the selector consumes at SA-4 to rank variants. The point of empirical calibration is to refuse the hack of selecting variants from spec-sheet cost models -- the only honest answer is "what does THIS device measure when we actually run the operations?" Composes: nx_probe -- capability fingerprint (caller's prior step) nx_clock -- monotonic-ns time helper nx_tier -- tier classification (NX_TIER_MCU..HPC inferred from the measurements) V1 microbenchmarks (SA-2 honest perf verdict): - int ALU ns/op (dependent-chain ADD, ~1M iterations) - pointer-chase latency at three working-set sizes (small ~ L1, medium ~ L2, large ~ RAM); cache-hierarchy witness via monotonic per-access latency increase - linear-copy memory bandwidth (bytes/ns over a large block) - syscall round-trip cost (clock_gettime loop, 10K calls) - mmap latency (10 mmap calls, ns/mmap) Gap list (V1): - FP ALU / vec ALU absent -- qemu-riscv64-static models them as scalar emulation; honest measurement requires real RV64 + RVV hardware OR the x86_64 + AVX2 native path (SA-2.5) - context-switch cost absent (fork/futex; deferred to SA-6 when nx_compile lands the fork primitive) - network RTT absent (no peer in smoke; SA-5) - energy per op absent (no RAPL access from substrate; SA-5+) - byzantine N-of-M deferred to SA-7 The substrate refuses these REFUSED HACKS per NISHI_SELF_ASSEMBLY_ROADMAP.md §6: - datasheet cost models (#7 refused) - single-axis selection from synthetic data (#3 refused) - vendor-supplied calibration (#14 refused)