nx_emu_riscv32.nx
buildroot/runtime/nx_emu_riscv32.nx
about
nx_emu_riscv32.nx -- sovereign RV32IM interpreter (NX-EMU, 32-bit XLEN).
Sibling of nx_emu_rv64 for the 32-bit RISC-V target; nxc2's rv32 backend
represents i64 as register PAIRS, so the KAT exercises add/sub/mul/mulhu/sltu
(carry) over 32-bit lanes. Flat little-endian guest RAM, Linux rv32 syscalls
(exit=93, a7=num, a0..=args). NO qemu -- decode/execute per the RISC-V ISA.
license_tier: ORIGINAL
dependencies 1 imports · 1 importers
imports: nx_syscalls_x86_64.nx
imported by: nx_isa_conform_gate.nx
structs
| none |
consts
| 9 | const R32_GUEST: i64 = 16777216 |
| 10 | const R32_MASK: i64 = 0xFFFFFFFF |
| 11 | const R32_SYS_EXIT: i64 = 93 |
| 14 | const R32_BIMM_SIGN: i64 = 4096 // bit 12 of the 13-bit offset |
| 15 | const R32_BIMM_SPAN: i64 = 8192 // 2 * R32_BIMM_SIGN -- subtract to sign-extend |
| 16 | const R32_BIMM_HI_MASK: i64 = 0x3f // imm[10:5] field |
| 17 | const R32_BIMM_LO_MASK: i64 = 0xf // imm[4:1] field |
| 18 | const R32_XLEN_BITS: i64 = 32 |
functions
| 20 | func r32_ld(mem: *u8, va: i64, width: i64) -> i64 called by 1: emu_riscv32_run_mem |
| 26 | func r32_st(mem: *u8, va: i64, width: i64, val: i64) -> i64 called by 1: emu_riscv32_run_mem |
| 31 | func r32_sx(v: i64, bits: i64) -> i64 { let m: i64 = 1 << (bits - 1); if (v & m) != 0 { return v - (1 << bits) } return v } called by 1: emu_riscv32_run_mem |
| 33 | func emu_riscv32_run_mem(mem: *u8, mem_size: i64, entry: i64, sp0: i64) -> i64 |
| 133 | func emu_riscv32_run(code: *u8, code_len: i64) -> i64 calls 1: emu_riscv32_run_mem |