nx_f32_hw_matmul_mac4.nx

nx_f32_hw_matmul_mac4.nx -- ILP matmul: 4 independent accumulators hide the addss latency. The single-acc inner loop serializes on `acc` (each addss waits ~4 cyc for the previous). Four independent accumulator chains let the CPU pipeline them -> up to ~4x if latency-bound -- and it is PURE .nx (scalar SSE via nx_f32_hw), so NO nx_cc change, NO rebuild, ZERO build risk. The safe win to bank BEFORE the risky packed-SIMD compiler surgery (which adds 4 lanes/instruction on top). Sum order differs from sequential, so f32 results can differ by ROUNDING -- but for small ints (exact) it is bit-identical to nx_f32_matmul/nx_f32_hw_matmul, so the KAT cross-checks exactly. Sovereign: imports nx_f32_hw_matmul (-> nx_f32_hw SSE) + nx_syscalls. license_tier: ORIGINAL