nx_f32_matmul_t.nx
buildroot/runtime/nx_f32_matmul_t.nx
about
nx_f32_matmul_t.nx -- matmul where B is laid out per ggml convention (B[k,j] at B[k + j*K]).
Same C[i,j] = sum_k A[i,k]*B[k,j] math. Inner MAC = sovereign SSE (__f32_add/__f32_mul, bit-identical IEEE f32).
SOVEREIGN MULTICORE (2026-06-18, operator "no 3rd party from the hardware rung up"): for big matmuls this
forks MMT_NW workers (sys_fork), each computing a flat output-range into a SHARED temp (sys_mmap_shared),
parent joins (sys_wait4) and copies the temp into C. Drop-in: same signature + output, C may be private (the
shared temp bridges). Pure syscalls -- NO libvulkan/CUDA/Mesa/pthread. Pattern proven in nx_par_matmul (6.78x,
bit-identical). Small matmuls stay serial (fork overhead not worth it).
genealogy_id: standard_matmul + ggml_dim_0_fast_layout + sovereign_fork_parallel
lineage_id: substrate_f32_matmul_t_v2_parallel
dependencies 5 imports · 15 importers
diagram shows first 10 each side; +0 more imports, +5 more importers in the complete lists below.
imports: nx_syscalls.nxnx_tier.nxnx_f32.nxnx_f32_matmul.nxnx_thread_pool.nx
imported by: nx_batchscale_kat.nxnx_f32_conv2d_backward_fast.nxnx_f32_conv2d_fast.nxnx_f32_ffn_path_gate.nxnx_f32_lazy_weight.nxnx_f32_llm_v4.nxnx_f32_matmul_t_test.nxnx_llm_layerlens_probe.nxnx_matmul_t_pool_gate.nxnx_matmul_tile_kat.nxnx_moe.nxnx_moe_gate.nxnx_q5_0_threaded_gate.nxnx_q8_0_simd_gate.nxnx_vit_encoder_layer.nx
structs
| 34 | struct NxMmtCtx |
consts
| 18 | const MMT_NW: i64 = 8 // worker forks |
| 19 | const MMT_PAR_MIN_MAC: i64 = 1000000000000000 // fork DISABLED: per-matmul fork was net-SLOWER in the forward (1300+ forks of a 491MB proc > the parallelism gain). Pool (fork-once) is the fix. Serial path (mmt_range) is the proven-correct SSE serial. |
| 45 | const NX_MMT_CTX_BYTES: i64 = 64 |
functions
| 49 | func _nx_mmt_tile_task(ctx_i: i64) -> i64 calls 1: mmt_tile_cols |
| 55 | func _nx_mmt_task(ctx_i: i64) -> i64 calls 1: mmt_range |
| 62 | func mmt_range(A: *i64, B: *i64, C: *i64, k: nx_int, n: nx_int, lo: i64, hi: i64) -> i64 |
| 98 | func mmt_tile_cols(A: *i64, B: *i64, C: *i64, m: i64, k: i64, n: i64, j0: i64, j1: i64) -> i64 |
| 125 | func nx_f32_matmul_t_tiled(A: *i64, B: *i64, C: *i64, |
| 134 | func nx_f32_matmul_t(A: *i64, B: *i64, C: *i64, |
| 170 | func nx_f32_matmul_t_pool(pool: *NxThreadPool, A: *i64, B: *i64, C: *i64, |