nx_isa_sparc64_gate.nx

nx_isa_sparc64_gate.nx -- THE SPARC64 CONFORMANCE RULER. WHY IT EXISTS: nx_isa_conform_gate measures five of the estate's ten sovereign ISA emulators and names the other five in one line -- "UNMEASURED: armv7a cortexm loongarch64 s390x sparc64 -- each owes a manual-derived KAT block here". This organ pays that debt for sparc64. It is a SEPARATE organ rather than an edit to the incumbent because five lanes are writing five arch blocks at once and concurrent edits to one file silently clobber each other in this tree; the shape is copied deliberately so the two rulers agree. THE LAW IT OBEYS: a capability asserted and never measured is a claim, not coverage. "We emulate sparc64" is decided by running SPARC V9 machine code, in process, against values taken FROM THE SPARC V9 MANUAL -- never from the emulator's own source, which would calibrate the ruler to the subject it exists to judge. The decoder was read first, but ONLY to learn which instruction classes are implemented versus missing; every expected value below is derived from the manual's encoding tables and its Bicc/BPcc condition table. WHAT THE READ FOUND, AND WHAT WAS BUILT BECAUSE OF IT. On 2026-09-03 nx_emu_sparc64 decoded CALL, SETHI, ADD/SUB/AND/OR/XOR, MULX, SDIVX/UDIVX, two shifts, SAVE/RESTORE, JMPL, Tcc and four load/store forms -- and NOTHING ELSE in format 2. It carried no condition-code state and no branch of any kind, so it could not run a LOOP: the sparc64 claim covered straight-line code only. Four further defects sat in the classes it did decode: 1. op3 0x08 is LDSW in V9 and was decoded as an UNSIGNED load, so the only 32-bit load available answered with the wrong sign extension; the real LDUW (op3 0x00) was absent entirely, so a correct program reported UNSUPPORTED. 2. SRL/SRLX (op3 0x26) was written with this dialect's arithmetic right shift and SRA/SRAX (op3 0x27) was absent -- so the logical and the arithmetic right shift were ONE expression and one of the two was necessarily wrong for every negative operand. 3. The shift count came from the sign-extended 13-bit simm without reading the X bit, so the 32-bit shift forms could not be told apart from the 64-bit ones. 4. No sub-word loads or stores at all (LDUB/LDSB/LDUH/LDSH/STB/STH). All of it was implemented in nx_emu_sparc64 -- condition codes for