nx_mask_geom.nx

nx_mask_geom.nx -- Arc D2: GDSII-class MASK GEOMETRY + DESIGN-RULE CHECK (the chip-fab equivalent of STL->G-code for the printer). The assignment generator queued this from the chip-fab research; this is the team building what it assigned itself. A mask is a set of rectangular FEATURES on a layer, in NANOMETER coordinates (nx_micron_geom). The S-class gate is DRC -- the design-rule check every real chip layout must pass before a fab will run it: * MIN WIDTH -- no feature thinner than the process can resolve (the critical dimension, CD) * MIN SPACING-- no two features closer than the process can separate (or they short together) * NO OVERLAP -- features on the same layer must not illegally intersect The CD ties straight to the CPU goal via nx_metrology: a layout is MAKEABLE only if the machine's resolution <= the layout's critical dimension (SUBMICRON makes transistors; FDM cannot). HONEST SCOPE: rectangles only (Manhattan); arbitrary polygons + the GDSII BINARY record emit are the flagged next rungs -- the geometry + DRC math here is exact. Rects stored as parallel i64 arrays x[],y[],w[],h[] (nm). LAWS: struct-free, integer-only. license_tier: ORIGINAL