code wiki / _hdl_build / nx_pcb_autoroute_gate.nx
nx_pcb_autoroute_gate.nx
buildroot/runtime/_hdl_build/nx_pcb_autoroute_gate.nx
about
nx_pcb_autoroute_gate.nx -- GATE for the SOVEREIGN PCB autorouter (reuses the silicon router = shared resource).
T1 CLEAN BOARD -- 2 non-conflicting nets route node-disjoint, 0 shorts, copper length>0.
T2 CROSS+DETOUR -- 2 nets that would cross at one node; node-keepout forces the 2nd to DETOUR, still routed, 0 shorts.
T3 NEVER-BRICK -- deterministic (re-run identical), bounded, pure memory.
T4 LIAR-KILL -- same crossing board WITHOUT keepout -> the traces SHORT (shorts>0); proves DRC keepout is load-bearing.
T5 CONGESTION -- a full-width trace blocks every vertical crossing -> the 2nd net is UNROUTABLE (not fabricated).
GREEN iff all pass. Sovereign nx_cc->nxasm (no gcc, no KiCad/Freerouting). expect_exit: 0 license_tier: ORIGINAL
dependencies 2 imports · 0 importers
imports: nx_pcb_autoroute.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 11 | func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 12 | func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 13 | func fill(a: *i64, n: i64, v: i64) -> i64 { var i: i64=0; while i<n { a[i]=v; i=i+1 } return 0 } called by 1: main |
| 15 | func main() -> i64 |