code wiki / _hdl_build / nx_pcb_drc_gate.nx
nx_pcb_drc_gate.nx
buildroot/runtime/_hdl_build/nx_pcb_drc_gate.nx
about
nx_pcb_drc_gate.nx -- GATE for the PCB DRC digital twin (real fab rules, real mils). Closes the omniforge ED "DRC" gap.
T1 MANUFACTURABLE -- two adjacent different-net traces at 12-mil pitch / 6-mil trace (gap=6) under the 6/6 rule -> 0 violations.
T2 CLEARANCE FAIL -- the SAME board at 10-mil pitch (gap=4 < 6) -> 2 clearance violations (the DRC catches the real short risk).
T3 WIDTH FAIL -- a 4-mil trace under the 6-mil width rule -> 1 width violation (too thin to etch reliably).
T4 NEVER-BRICK -- empty board = 0 violations; deterministic re-run.
T5 ROUTE+DRC TWIN -- route a real 2-net board on the shared router, DRC it at the standard fab class -> 0 (manufacturable).
GREEN iff all pass. Sovereign nx_cc->nxasm, no 3rd-party. expect_exit: 0 license_tier: ORIGINAL
dependencies 3 imports · 0 importers
imports: nx_pcb_drc.nxnx_pcb_autoroute.nxnx_syscalls.nx
imported by: nobody (leaf or entry point)
call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown
structs
| none |
consts
| none |
functions
| 12 | func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } |
| 13 | func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } |
| 14 | func fill(a: *i64, n: i64, v: i64) -> i64 { var i: i64=0; while i<n { a[i]=v; i=i+1 } return 0 } called by 1: main |
| 16 | func main() -> i64 |